index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
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log msg
author
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path:
root
/
drivers
/
fpga
/
xilinx-spi.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-03-31
fpga: xilinx-spi: extract a common driver core
Charles Perry
1
-209
/
+15
2021-11-29
fpga: mgr: Use standard dev_release for class driver
Russ Weight
1
-7
/
+4
2021-07-25
fpga: xiilnx-spi: Address warning about unused variable
Moritz Fischer
1
-0
/
+2
2021-03-24
fpga: fpga-mgr: xilinx-spi: fix error messages on -EPROBE_DEFER
Luca Ceresoli
1
-15
/
+9
2020-12-01
fpga: fpga-mgr: xilinx-spi: Simplify registration
Moritz Fischer
1
-13
/
+1
2020-08-31
fpga manager: xilinx-spi: provide better diagnostics on programming failure
Luca Ceresoli
1
-1
/
+15
2020-08-31
fpga manager: xilinx-spi: add error checking after gpiod_get_value()
Luca Ceresoli
1
-8
/
+27
2020-08-31
fpga manager: xilinx-spi: fix write_complete timeout handling
Luca Ceresoli
1
-8
/
+15
2020-08-31
fpga manager: xilinx-spi: remove final dot from dev_err() strings
Luca Ceresoli
1
-2
/
+2
2020-08-20
fpga manager: xilinx-spi: remove stray comment
Luca Ceresoli
1
-1
/
+0
2020-06-27
fpga manager: xilinx-spi: check INIT_B pin during write_init
Luca Ceresoli
1
-1
/
+54
2020-06-19
fpga manager: xilinx-spi: remove unneeded, mistyped variables
Luca Ceresoli
1
-4
/
+2
2020-06-19
fpga manager: xilinx-spi: valid for the 7 Series too
Luca Ceresoli
1
-1
/
+1
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422
Thomas Gleixner
1
-4
/
+1
2018-10-16
fpga: mgr: add devm_fpga_mgr_create
Alan Tull
1
-8
/
+4
2018-05-25
fpga: manager: change api, don't use drvdata
Alan Tull
1
-3
/
+17
2017-04-08
fpga manager: Add Xilinx slave serial SPI driver
Anatolij Gustschin
1
-0
/
+198