starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-12-02	module: Convert symbol namespace to string literal	Peter Zijlstra	1	-1/+1
2024-09-04	cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()	Li Ming	1	-1/+1
2024-09-04	cxl/port: Use scoped_guard()/guard() to drop device_lock() for cxl_port	Li Ming	1	-12/+10
2024-09-04	cxl/port: Use __free() to drop put_device() for cxl_port	Li Ming	1	-3/+2
2024-07-28	Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...	Linus Torvalds	1	-0/+1
2024-07-02	cxl: add missing MODULE_DESCRIPTION() macros	Jeff Johnson	1	-0/+1
2024-06-19	cxl/mem: Fix no cxl_nvd during pmem region auto-assembling	Li Ming	1	-8/+9
2024-02-17	cxl: Fix sysfs export of qos_class for memdev	Dave Jiang	1	-36/+0
2024-02-17	cxl: Change 'struct cxl_memdev_state' *_perf_list to single 'struct cxl_dpa_p...	Dave Jiang	1	-24/+4
2023-12-23	cxl: Export sysfs attributes for memory device QoS class	Dave Jiang	1	-6/+61
2023-10-28	cxl/pci: Add RCH downstream port AER register discovery	Robert Richter	1	-0/+2
2023-10-28	cxl/hdm: Use stored Component Register mappings to map HDM decoder capability	Robert Richter	1	-3/+2
2023-06-26	Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl	Dan Williams	1	-13/+3
2023-06-26	cxl/mbox: Move mailbox related driver state to its own data structure	Dan Williams	1	-3/+7
2023-06-25	cxl/pci: Early setup RCH dport component registers from RCRB	Robert Richter	1	-9/+0
2023-06-25	cxl/mem: Prepare for early RCH dport component register setup	Robert Richter	1	-5/+4
2023-06-25	cxl: Rename 'uport' to 'uport_dev'	Dan Williams	1	-1/+1
2023-06-25	cxl/acpi: Probe RCRB later during RCH downstream port creation	Robert Richter	1	-2/+2
2023-05-19	cxl: Move cxl_await_media_ready() to before capacity info retrieval	Dave Jiang	1	-0/+3
2023-04-23	cxl/mem: Add debugfs attributes for poison inject and clear	Alison Schofield	1	-0/+28
2023-04-23	cxl/memdev: Add trigger_poison_list sysfs attribute	Alison Schofield	1	-0/+43
2022-12-05	cxl/port: Add RCD endpoint port enumeration	Dan Williams	1	-8/+25
2022-12-05	cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem	Dan Williams	1	-0/+38
2022-12-03	cxl/pmem: Refactor nvdimm device registration, delete the workqueue	Dan Williams	1	-0/+9
2022-07-22	cxl/mem: Enumerate port targets before adding endpoints	Dan Williams	1	-29/+1
2022-07-22	cxl/port: Record parent dport when adding ports	Dan Williams	1	-4/+6
2022-07-10	cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'	Dan Williams	1	-0/+23
2022-06-22	cxl: Fix cleanup of port devices on failure to probe driver.	Jonathan Cameron	1	-1/+6
2022-05-19	cxl/port: Move endpoint HDM Decoder Capability init to port driver	Dan Williams	1	-11/+0
2022-05-19	cxl/pci: Drop @info argument to cxl_hdm_decode_init()	Dan Williams	1	-2/+1
2022-05-19	cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()	Dan Williams	1	-79/+1
2022-05-19	cxl/mem: Skip range enumeration if mem_enable clear	Dan Williams	1	-1/+1
2022-05-19	cxl/mem: Consolidate CXL DVSEC Range enumeration in the core	Dan Williams	1	-6/+8
2022-05-19	cxl/pci: Move cxl_await_media_ready() to the core	Dan Williams	1	-1/+1
2022-05-19	cxl/mem: Validate port connectivity before dvsec ranges	Dan Williams	1	-16/+16
2022-05-19	cxl/mem: Fix cxl_mem_probe() error exit	Dan Williams	1	-2/+4
2022-05-19	cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()	Dan Williams	1	-18/+1
2022-05-19	cxl/mem: Drop mem_enabled check from wait_for_media()	Dan Williams	1	-4/+0
2022-04-29	cxl: Drop cxl_device_lock()	Dan Williams	1	-2/+2
2022-04-23	PM: CXL: Disable suspend	Dan Williams	1	-1/+21
2022-04-13	cxl/mem: Replace redundant debug message with a comment	Dan Williams	1	-4/+10
2022-04-13	cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()	Dan Williams	1	-6/+6
2022-04-13	cxl/mem: Make cxl_dvsec_range() init failure fatal	Dan Williams	1	-0/+3
2022-04-13	cxl/mem: Drop DVSEC vs EFI Memory Map sanity check	Dan Williams	1	-23/+1
2022-02-09	cxl/mem: Add the cxl_mem driver	Ben Widawsky	1	-0/+228
2021-05-26	cxl: Rename mem to pci	Ben Widawsky	1	-1525/+0
2021-05-15	cxl/core: Refactor CXL register lookup for bridge reuse	Dan Williams	1	-44/+6
2021-05-15	cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices	Dan Williams	1	-20/+24
2021-05-15	cxl/mem: Move some definitions to mem.h	Dan Williams	1	-20/+1
2021-04-17	cxl/mem: Fix memory device capacity probing	Dan Williams	1	-2/+5