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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)AuthorFilesLines
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-25/+32
2023-06-26Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+16
2023-06-26Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams1-7/+9
2023-06-26Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-6/+5
2023-06-26Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-1/+0
2023-06-26cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams1-1/+1
2023-06-26cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-2/+2
2023-06-26cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams1-2/+2
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams1-0/+8
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams1-7/+1
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+2
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+2
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+2
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-2/+0
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-0/+1
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-4/+6
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-6/+7
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter1-2/+2
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-2/+7
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-9/+3
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+13
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron1-0/+3
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso1-0/+8
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-0/+1
2023-04-05cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams1-2/+2
2023-04-05cxl/hdm: Skip emulation when driver manages mem_enableDan Williams1-1/+3
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-2/+94
2023-02-15Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-2/+18
2023-02-15cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-1/+2
2023-02-15cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+2
2023-02-15cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-0/+14
2023-02-15Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-0/+1
2023-02-15cxl: add RAS status unmasking for CXLDave Jiang1-0/+1
2023-02-11Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-0/+57
2023-02-11cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-0/+12
2023-02-11tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-0/+2
2023-02-11cxl/region: Add region autodiscoveryDan Williams1-0/+29
2023-02-11cxl/region: Add a mode attribute for regionsDan Williams1-0/+14
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman1-2/+2
2023-01-27cxl/mem: Wire up event interruptsDavidlohr Bueso1-0/+4
2023-01-27cxl/mem: Read, trace, and clear events on driver loadIra Weiny1-0/+12
2023-01-05cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+2
2022-12-06cxl: update names for interleave ways conversion macrosDave Jiang1-7/+7
2022-12-06cxl: update names for interleave granularity conversion macrosDave Jiang1-6/+7
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-2/+9
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-9/+29
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams1-0/+11
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams1-2/+0
2022-12-04cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield1-2/+9
2022-12-04cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+1
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