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path: root/drivers/cxl/cxl.h
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2021-11-08Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-19/+39
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams1-0/+10
2021-09-25cxl/core: Replace unions with struct_group()Kees Cook1-43/+18
2021-09-22cxl/core: Split decoder setup into alloc + addDan Williams1-9/+6
2021-09-22tools/testing/cxl: Introduce a mock memory device + driverDan Williams1-1/+1
2021-09-22cxl/bus: Populate the target list at decoder createDan Williams1-15/+10
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-0/+16
2021-09-21cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams1-0/+2
2021-08-06cxl/pci: Simplify register setupBen Widawsky1-1/+0
2021-06-16cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-1/+11
2021-06-16cxl/pmem: Add initial infrastructure for pmem supportDan Williams1-0/+24
2021-06-16cxl/core: Add cxl-bus driver infrastructureDan Williams1-0/+22
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky1-0/+7
2021-06-10cxl/acpi: Introduce cxl_decoder objectsDan Williams1-0/+63
2021-06-10cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-0/+21
2021-06-10cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+31
2021-06-06cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-6/+59
2021-06-06cxl/pci: Map registers based on capabilitiesIra Weiny1-5/+28
2021-05-15cxl/core: Refactor CXL register lookup for bridge reuseDan Williams1-0/+3
2021-05-15cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams1-0/+32
2021-05-15cxl/mem: Move some definitions to mem.hDan Williams1-57/+0
2021-02-17cxl/mem: Enable commands via CELBen Widawsky1-0/+2
2021-02-17cxl/mem: Register CXL memX devicesDan Williams1-0/+3
2021-02-17cxl/mem: Find device capabilitiesBen Widawsky1-0/+90
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-28 09:39:22 +0300