starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-06-07	driver/include/sound: Normalize the copyright licenses	Xingyu Wu	9	-9/+18
2023-01-13	clk: starfive: Fixed UART3-5 error after resume	Xingyu Wu	1	-5/+6
2023-01-11	clk: starfive: Add funtions of saving and restoring data about SYS, AON and STG	Xingyu Wu	2	-0/+185
2022-12-15	clk: starfive: pll: Remove high frequency of PLL0	Xingyu Wu	1	-23/+3
2022-12-15	clk: starfive: Change divider value of cpu_core clock	Xingyu Wu	1	-1/+1
2022-11-14	clk:starfive:vout:Add parent about disp_apb clk	Xingyu Wu	1	-2/+2
2022-11-14	clk:starfive:vout:Add runtime and system pm	Xingyu Wu	2	-38/+111
2022-11-01	clk: starfive: Keep the clock apb0 enabled always	Hal Feng	1	-1/+1
2022-10-28	Merge branch 'CR_2412_515_Clocktree_PLL1_Xingyu.Wu' into 'jh7110-5.15.y-devel'	andy.hu	2	-7/+1
2022-10-28	Merge branch 'CR_2440_515_Clocktree_1.5G_Xingyu.Wu' into 'jh7110-5.15.y-devel'	andy.hu	2	-0/+36
2022-10-27	clk:starfive:isp:Add runtime and system pm control	Xingyu Wu	3	-43/+126
2022-10-26	clk:starfive:Count PLL1 rate	Xingyu Wu	2	-7/+1
2022-10-26	clk:starfive:Change PLL0 rate to 1.5GHz	Xingyu Wu	2	-0/+36
2022-09-06	clk:starfive:Set pll2 default rate to 1188m	Xingyu Wu	1	-1/+1
2022-08-19	clk:starfive:Modify 'stg_apb' clock	Xingyu Wu	1	-6/+5
2022-07-20	clk:starfive:Update clk and reset api about vout	xingyu.wu	1	-37/+22
2022-07-20	clk:starfive:Update clk and reset api about isp	xingyu.wu	1	-105/+31
2022-07-20	clk:starfive:Modify function format about 'jh7110_pll_data_from'	xingyu.wu	1	-2/+2
2022-07-20	clk:starfive:Set PLL2 frequency when clock tree registering	xingyu.wu	2	-1/+14
2022-07-20	clk:starfive:Add PLL2 frequency controller	xingyu.wu	4	-25/+35
2022-07-20	clk:starfive:Add PLL0 frequency controller	xingyu.wu	7	-2/+765
2022-07-20	clk:starfive:Modify the format	xingyu.wu	7	-110/+119
2022-07-20	dt-bindings:clock:Delete external clock definitions	xingyu.wu	5	-0/+40
2022-07-01	clk:starfive:Update pmu Api	xingyu.wu	2	-4/+14
2022-06-08	clk:starfive:jh7110: Change uart3-uart5 clk register info	yanhong.wang	2	-3/+13
2022-05-30	clk:starfive:Adjust clocks' flag	xingyu.wu	1	-18/+18
2022-05-25	Merge branch 'CR_1051_CLOCK_TREE_Xingyu.Wu' into 'jh7110-5.15.y-devel'	andy.hu	2	-36/+40
2022-05-24	clk:starfive:Modify the definitions instead of numbers in vout clock tree	xingyu.wu	1	-14/+18
2022-05-24	clk:starfive:Modify the critical clocks' flags	xingyu.wu	1	-22/+22
2022-05-23	Merge branch 'CR_1035_CLOCK_TREE_VOUT_Xingyu.Wu' into 'jh7110-5.15.y-devel'	andy.hu	1	-1/+65
2022-05-23	clk:starfive:jh7110: pll0 switches to 1250M.	samin	1	-1/+1
2022-05-20	clk:starfive:Add top clocks and reset in vout clock tree	xingyu.wu	1	-1/+65
2022-05-17	clk:starfive:Change some clocks to 'ignore-unused'	xingyu.wu	4	-17/+17
2022-05-15	clk:starfive:Change PLL0 dafalut value from 1250m to 1000m	xingyu.wu	1	-1/+1
2022-05-15	driver:clk:Add noc clock initialization in isp clock tree driver	xingyu.wu	1	-8/+72
2022-05-15	clk:starfive:Modify the clock to 'CLK_IGNORE_UNUSED' flag	xingyu.wu	3	-52/+52
2022-05-15	clktree: jh7110: disable jh7110_clk_disable function interface.	samin	1	-2/+2
2022-04-28	clk:starfive: Add definition instead of numbers	xingyu.wu	5	-195/+230
2022-04-28	clk:starfive: Add isp clock tree driver	xingyu.wu	4	-0/+296
2022-04-24	risv:dts:starfive:Add timer clocktree	xingyu.wu	1	-5/+5
2022-04-19	clk:starfive: Adjust the format	xingyu.wu	6	-526/+526
2022-04-13	arch:riscv:Kconfig: Add choice with SOC board type	xingyu.wu	5	-24/+26
2022-04-13	clk:starfive: Add vout clock tree driver	xingyu.wu	4	-0/+281
2022-04-13	clk:starfive: Add JH7110 clock tree driver for kernel 5.15	xingyu.wu	9	-0/+1643
2021-10-30	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds	1	-5/+5
2021-10-18	clk: composite: Also consider .determine_rate for rate + mux composites	Martin Blumenstingl	1	-5/+5
2021-10-13	clk: qcom: add select QCOM_GDSC for SM6350	Luca Weiss	1	-0/+1
2021-10-13	clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdsc	Shawn Guo	1	-1/+1
2021-09-29	Merge tag 'renesas-clk-for-v5.15-tag3' of git://git.kernel.org/pub/scm/linux/...	Stephen Boyd	2	-1/+3
2021-09-25	clk: socfpga: agilex: fix duplicate s2f_user0_clk	Dinh Nguyen	1	-9/+0