starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-12-15	clk: tegra: Support runtime PM and power domain	Dmitry Osipenko	1	-31/+85
2021-05-31	clk: tegra: Don't deassert reset on enabling clocks	Dmitry Osipenko	1	-1/+1
2021-05-31	clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling	Dmitry Osipenko	1	-1/+1
2021-05-31	clk: tegra30: Use 300MHz for video decoder by default	Dmitry Osipenko	1	-1/+1
2021-02-22	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-4/+1
2021-02-11	clk: tegra: clk-tegra30: Remove unused variable 'reg'	Lee Jones	1	-4/+1
2021-01-12	clk: tegra30: Add hda clock default rates to clock driver	Peter Geis	1	-0/+2
2020-05-12	clk: tegra30: Use custom CCLK implementation	Dmitry Osipenko	1	-2/+4
2020-03-12	clk: tegra: Remove audio clocks configuration from clock driver	Sowjanya Komatineni	1	-3/+2
2020-03-12	clk: tegra: Remove tegra_pmc_clk_init along with clk ids	Sowjanya Komatineni	1	-15/+3
2020-03-12	clk: tegra: Remove CLK_M_DIV fixed clocks	Sowjanya Komatineni	1	-4/+0
2020-03-12	clk: tegra: Add Tegra OSC to clock lookup	Sowjanya Komatineni	1	-0/+2
2020-03-12	clk: tegra: Add support for OSC_DIV fixed clocks	Sowjanya Komatineni	1	-0/+4
2020-01-10	clk: tegra20/30: Explicitly set parent clock for Video Decoder	Dmitry Osipenko	1	-1/+1
2020-01-10	clk: tegra20/30: Don't pre-initialize displays parent clock	Dmitry Osipenko	1	-2/+0
2019-11-11	clk: tegra: Optimize PLLX restore on Tegra20/30	Dmitry Osipenko	1	-9/+16
2019-11-11	clk: tegra: Add Tegra20/30 EMC clock implementation	Dmitry Osipenko	1	-11/+27
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner	1	-12/+1
2018-12-15	clk: tegra30: Use Tegra CPU powergate helper function	Jon Hunter	1	-3/+3
2018-12-15	clk: tegra: Fix maximum audio sync clock for Tegra124/210	Jon Hunter	1	-1/+8
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko	1	-1/+1
2018-03-12	clk: tegra: Specify VDE clock rate	Dmitry Osipenko	1	-0/+1
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko	1	-10/+4
2017-11-01	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	1	-1/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	1	-0/+1
2017-10-19	clk: tegra: Make tegra_clk_pll_params __ro_after_init	Bhumika Goyal	1	-8/+8
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	1	-3/+1
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver	1	-0/+1
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	1	-111/+2
2016-04-28	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	Lucas Stach	1	-5/+6
2016-04-28	clk: tegra: Initialize PLL_C to sane rate on Tegra30	Lucas Stach	1	-0/+1
2015-11-20	clk: tegra: pll: Update PLLM handling	Danny Huang	1	-1/+1
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein	1	-110/+117
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein	1	-9/+15
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-1/+1
2015-11-18	clk: tegra: Format tables consistently	Thierry Reding	1	-189/+189
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding	1	-10/+5
2015-11-18	clk: tegra: Fix 26 MHz oscillator frequency	Thierry Reding	1	-1/+1
2015-10-20	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein	1	-1/+7
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd	1	-1/+0
2015-05-13	clk: tegra: Fix hda2codec_2x clock name for Tegra30	Marcel Ziswiler	1	-1/+1
2015-04-10	clk: tegra: Model oscillator as clock	Thierry Reding	1	-1/+2
2015-04-10	clk: tegra: Use consistent indentation	Thierry Reding	1	-10/+10
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding	1	-1/+6
2014-07-17	ARM: tegra: Convert PMC to a driver	Thierry Reding	1	-1/+1
2014-07-17	ARM: tegra: Move includes to include/soc/tegra	Thierry Reding	1	-1/+4
2013-12-12	clk: tegra: remove bogus PCIE_XCLK	Stephen Warren	1	-7/+0
2013-12-12	clk: tegra: implement a reset driver	Stephen Warren	1	-1/+2
2013-11-26	clk: tegra: add FUSE clock device	Alexandre Courbot	1	-1/+1
2013-11-26	clk: tegra: Properly setup PWM clock on Tegra30	Thierry Reding	1	-1/+3