starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-12-15	clk: tegra: Support runtime PM and power domain	Dmitry Osipenko	1	-1/+1
2021-05-31	clk: tegra: Don't allow zero clock rate for PLLs	Dmitry Osipenko	1	-0/+3
2021-05-31	clk: tegra: Ensure that PLLU configuration is applied properly	Dmitry Osipenko	1	-5/+4
2021-03-24	clk: tegra: Don't enable PLLE HW sequencer at init	JC Kuo	1	-12/+0
2020-09-21	clk: tegra: Always program PLL_E when enabled	Thierry Reding	1	-3/+0
2020-09-21	clk: tegra: Capitalization fixes	Thierry Reding	1	-2/+2
2020-07-28	clk: tegra: pll: Improve PLLM enable-state detection	Dmitry Osipenko	1	-5/+15
2020-05-12	clk: tegra: pll: Add pre/post rate-change hooks	Dmitry Osipenko	1	-1/+11
2019-11-11	clk: tegra: pll: Save and restore pll context	Sowjanya Komatineni	1	-32/+54
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner	1	-12/+1
2019-04-25	clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider	Dmitry Osipenko	1	-2/+2
2019-04-20	clk: tegra: Don't enable already enabled PLLs	Dmitry Osipenko	1	-13/+37
2018-12-15	clk: tegra: Return the exact clock rate from clk_round_rate	Robert Yang	1	-3/+4
2018-03-12	clk: tegra: Fix pll_u rate configuration	Marcel Ziswiler	1	-0/+2
2017-08-24	clk: tegra: Fix T210 PLLRE registration	Alex Frid	1	-20/+1
2017-08-24	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid	1	-39/+9
2017-08-24	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	1	-40/+0
2017-08-24	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver	1	-1/+1
2017-08-24	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver	1	-0/+2
2017-08-24	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver	1	-1/+1
2017-08-24	clk: tegra: fix SS control on PLL enable/disable	Peter De Schrijver	1	-20/+24
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver	1	-174/+0
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	1	-0/+505
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	1	-0/+46
2016-02-02	clk: tegra: Fix PLLE SS coefficients	Mark Kuo	1	-6/+12
2016-02-02	clk: tegra: Fix typos around clearing PLLE bits during enable	Rhyland Klein	1	-2/+2
2016-02-02	clk: tegra: Do not disable PLLE when under hardware control	Mark Kuo	1	-7/+15
2016-02-02	clk: tegra: pll: Fix potential sleeping-while-atomic	Andrew Bresticker	1	-3/+3
2015-12-17	clk: tegra: Read correct IDDQ register in PLL_SS registration	Bill Huang	1	-4/+7
2015-12-17	clk: tegra: Fix WARN_ON in PLL_RE registration	Bill Huang	1	-1/+2
2015-12-17	clk: tegra: pll: Fix issues with rates for VCO PLLs	Andrew Bresticker	1	-4/+12
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	1	-0/+5
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang	1	-1/+24
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein	1	-0/+7
2015-12-17	clk: tegra: pll: Add Set_default logic	Bill Huang	1	-11/+28
2015-12-17	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang	1	-0/+28
2015-12-17	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein	1	-5/+43
2015-12-17	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein	1	-2/+322
2015-11-20	clk: tegra: pll: Update PLLM handling	Danny Huang	1	-49/+7
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein	1	-41/+50
2015-11-20	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang	1	-0/+12
2015-11-20	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein	1	-2/+22
2015-11-20	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein	1	-1/+65
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein	1	-9/+2
2015-11-20	clk: tegra: pll: Update warning message	Rhyland Klein	1	-1/+2
2015-11-20	clk: tegra: pll: Simplify clk_enable_path	Rhyland Klein	1	-54/+22
2015-11-20	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein	1	-0/+5
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-3/+3
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding	1	-3/+3
2015-08-25	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	Stephen Boyd	1	-4/+4