index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
/
clk-dfll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2019-03-14
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-9
/
+9
2019-02-22
clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings
YueHaibing
1
-9
/
+9
2019-02-06
clk: tegra: dfll: round down voltages based on alignment
Joseph Lo
1
-8
/
+13
2019-02-06
clk: tegra: dfll: support PWM regulator control
Joseph Lo
1
-67
/
+377
2018-11-29
clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro
Yangtao Li
1
-11
/
+1
2018-10-17
clk: tegra: probe deferral error reporting
Marcel Ziswiler
1
-2
/
+6
2018-06-02
clk: tegra: no need to check return value of debugfs_create functions
Greg Kroah-Hartman
1
-31
/
+11
2017-11-01
clk: tegra: dfll: Fix drvdata overwriting issue
Nicolin Chen
1
-5
/
+5
2017-01-30
PM / OPP: Update OPP users to put reference
Viresh Kumar
1
-11
/
+6
2016-04-28
clk: tegra: dfll: Reference CVB table instead of copying data
Thierry Reding
1
-5
/
+6
2016-03-03
clk: tegra: Remove CLK_IS_ROOT
Stephen Boyd
1
-1
/
+0
2015-10-20
Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Michael Turquette
1
-57
/
+57
2015-10-20
clk: tegra: dfll: Monitor code is DEBUG_FS only
Thierry Reding
1
-50
/
+49
2015-09-17
clk: tegra: dfll: Properly protect OPP list
Thierry Reding
1
-1
/
+7
2015-09-15
clk: tegra: Unlock top rates for Tegra124 DFLL clock
Mikko Perttunen
1
-7
/
+8
2015-08-26
clk: tegra: Fix some static checker problems
Stephen Boyd
1
-3
/
+5
2015-07-16
clk: tegra: Add Tegra124 DFLL clocksource platform driver
Tuomas Tynkkynen
1
-3
/
+3
2015-07-16
clk: tegra: Add closed loop support for the DFLL
Tuomas Tynkkynen
1
-3
/
+663
2015-07-16
clk: tegra: Add library for the DFLL clock source (open-loop mode)
Tuomas Tynkkynen
1
-0
/
+1095