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path: root/drivers/clk/sprd
AgeCommit message (Expand)AuthorFilesLines
2020-04-03clk: sprd: fix to get a correct ibias of pllChunyan Zhang1-3/+4
2020-03-25clk: sprd: add clocks support for SC9863AChunyan Zhang3-0/+1781
2020-03-25clk: sprd: support to get regmap from parent nodeChunyan Zhang1-1/+9
2020-03-25clk: sprd: Add macros for referencing parents without stringsChunyan Zhang5-55/+196
2020-03-25clk: sprd: add gate for pll clocksXiaolong Zhang2-2/+36
2019-11-27Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and ...Stephen Boyd1-1/+1
2019-11-14clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_...Baolin Wang1-1/+1
2019-10-17clk: sprd: Change to use devm_platform_ioremap_resource()Baolin Wang1-3/+1
2019-09-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-2/+5
2019-09-20Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-nextStephen Boyd1-0/+2
2019-09-18clk: sprd: add missing kfreeChunyan Zhang1-0/+2
2019-08-16clk: sprd: Don't reference clk_init_data after registrationStephen Boyd1-2/+3
2019-07-23clk: sprd: Select REGMAP_MMIO to avoid compile errorsChunyan Zhang1-0/+1
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-3/+11
2019-06-28clk: sprd: Add check for return value of sprd_clk_regmap_init()Chunyan Zhang1-1/+4
2019-06-26clk: sprd: Check error only for devm_regmap_init_mmio()Chunyan Zhang1-1/+1
2019-06-26clk: sprd: Switch from of_iomap() to devm_ioremap_resource()Chunyan Zhang1-1/+6
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
2019-05-01clk: sprd: Use the correct style for SPDX License IdentifierNishad Kamdar6-6/+6
2018-03-17clk: sprd: add RTC gate for SC9860Chunyan Zhang1-0/+76
2018-01-27Merge branch 'clk-divider-container' into clk-nextStephen Boyd1-1/+2
2017-12-22clk: sprd: add clocks support for SC9860Chunyan Zhang3-0/+1987
2017-12-22clk: sprd: add adjustable pll supportChunyan Zhang3-0/+375
2017-12-22clk: sprd: add composite clock supportChunyan Zhang3-0/+112
2017-12-22clk: sprd: add divider clock supportChunyan Zhang3-0/+166
2017-12-22clk: sprd: add mux clock supportChunyan Zhang3-0/+151
2017-12-22clk: sprd: add gate clock supportChunyan Zhang3-0/+171
2017-12-22clk: sprd: Add common infrastructureChunyan Zhang4-0/+141