| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-06-20 | clk: socfpga: Fix the smplsel on Arria10 and Stratix10 | Dinh Nguyen | 1 | -0/+3 |
| 2015-08-25 | clk: socfpga: Add a second parent option for the dbg_base_clk | Dinh Nguyen | 1 | -0/+1 |
| 2015-07-28 | clk: socfpga: switch to GENMASK() | Andy Shevchenko | 1 | -1/+0 |
| 2015-07-20 | clk: socfpga: Remove clk.h and clkdev.h includes | Stephen Boyd | 1 | -1/+0 |
| 2015-05-22 | clk: socfpga: add a clock driver for the Arria 10 platform | Dinh Nguyen | 1 | -0/+5 |
| 2015-05-22 | clk: socfpga: update clk.h so for Arria10 platform to use | Dinh Nguyen | 1 | -1/+5 |
| 2014-05-12 | clk: socfpga: add divider registers to the main pll outputs | Dinh Nguyen | 1 | -0/+4 |
| 2014-02-19 | clk: socfpga: split clk code | Steffen Trumtrar | 1 | -0/+57 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |