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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
socfpga
/
clk-gate.c
Age
Commit message (
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)
Author
Files
Lines
2021-04-28
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' a...
Stephen Boyd
1
-5
/
+8
2021-03-31
clk: socfpga: use clk_hw_register for a5/c5
Dinh Nguyen
1
-4
/
+7
2021-03-29
clk: socfpga: fix iomem pointer cast on 64-bit
Krzysztof Kozlowski
1
-1
/
+1
2019-08-16
clk: socfpga: deindent code to proper indentation
Stephen Boyd
1
-2
/
+2
2019-08-16
clk: socfpga: Don't reference clk_init_data after registration
Stephen Boyd
1
-10
/
+12
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Thomas Gleixner
1
-11
/
+1
2019-01-24
clk: socfpga: Don't have get_parent for single parent ops
Stephen Boyd
1
-9
/
+13
2015-07-28
clk: socfpga: switch to GENMASK()
Andy Shevchenko
1
-1
/
+1
2015-07-20
clk: socfpga: Remove clk.h and clkdev.h includes
Stephen Boyd
1
-2
/
+1
2015-06-06
clk: socfpga: make use of of_clk_parent_fill helper function
Dinh Nguyen
1
-5
/
+1
2015-05-22
clk: socfpga: update clk.h so for Arria10 platform to use
Dinh Nguyen
1
-4
/
+0
2015-05-15
clk: socfpga: Silence sparse warning
Stephen Boyd
1
-1
/
+1
2014-05-12
clk: socfpga: add divider registers to the main pll outputs
Dinh Nguyen
1
-1
/
+0
2014-02-19
clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
Dinh Nguyen
1
-0
/
+68
2014-02-19
clk: socfpga: split clk code
Steffen Trumtrar
1
-0
/
+195