starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-03-21	clk: rockchip: support more core div setting	Elaine Zhang	1	-6/+8
2021-02-06	clk: rockchip: fix DPHY gate locations on rk3368	Heiko Stuebner	1	-2/+2
2021-02-06	clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368	Heiko Stuebner	1	-1/+1
2021-02-06	clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368	Heiko Stuebner	1	-2/+2
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-9/+3
2019-06-15	clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro	Heiko Stuebner	1	-9/+3
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	1	-10/+1
2019-05-15	clk: Remove io.h from clk-provider.h	Stephen Boyd	1	-0/+1
2017-10-14	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	Romain Perier	1	-1/+1
2017-06-02	clk: rockchip: mark some special clk as critical on rk3368	Elaine Zhang	1	-1/+4
2017-03-10	clk: rockchip: mark some rk3368 core-clks as critical	Elaine Zhang	1	-0/+3
2017-03-10	clk: rockchip: export SCLK_TIMERXX id for timers on rk3368	Elaine Zhang	1	-12/+12
2016-03-27	clk: rockchip: release io resource when failing to init clk	Shawn Lin	1	-0/+1
2016-03-27	clk: rockchip: Add support for multiple clock providers	Xing Zheng	1	-7/+14
2016-03-27	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	Xing Zheng	1	-0/+6
2016-03-04	Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/g...	Stephen Boyd	1	-37/+60
2016-02-26	clk: rockchip: include downstream muxes into fractional dividers on rk3368	Elaine Zhang	1	-37/+60
2016-02-15	Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Michael Turquette	1	-49/+33
2016-02-04	clk: rockchip: convert manually created factor clocks to the new type	Heiko Stuebner	1	-22/+6
2016-01-25	clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch	zhangqing	1	-1/+1
2016-01-25	clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch	zhangqing	1	-1/+1
2016-01-25	clk: rockchip: rk3368: fix edp_24m parent	zhangqing	1	-1/+1
2016-01-25	clk: rockchip: rk3368: fix hdmi_cec gate-register	Heiko Stuebner	1	-1/+1
2016-01-25	clk: rockchip: rk3368: fix parents of video encoder/decoder	Heiko Stuebner	1	-2/+2
2016-01-25	clk: rockchip: rk3368: fix cpuclk core dividers	Heiko Stuebner	1	-20/+20
2016-01-25	clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster	Heiko Stuebner	1	-1/+1
2016-01-16	clk: rockchip: rk3368: fix some clock gates	Jianqun xu	1	-13/+13
2015-12-21	clk: rockchip: only enter pll slow-mode directly before reboots on rk3288	Heiko Stuebner	1	-1/+1
2015-12-03	clk: rockchip: fix rk3368 cpuclk divider offsets	Heiko Stuebner	1	-2/+2
2015-12-03	clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocks	Jianqun xu	1	-0/+2
2015-12-02	clk: rockchip: Force rk3368 PWM clock (and its parents) on	Caesar Wang	1	-0/+5
2015-09-14	clk: rockchip: add critical clock for rk3368	Heiko Stübner	1	-0/+6
2015-07-07	clk: rockchip: add rk3368 clock controller	Heiko Stuebner	1	-0/+881