starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-07-05	clk: renesas: r9a07g043: Add support for RZ/Five SoC	Lad Prabhakar	1	-0/+32
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	1	-0/+2
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	1	-12/+6
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	1	-2/+1
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	1	-6/+4
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for ADC	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add TSU clock and reset entry	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add RSPI clock and reset entries	Biju Das	1	-0/+9
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...	Biju Das	1	-0/+18
2022-04-28	clk: renesas: r9a07g043: Add WDT clock and reset entries	Biju Das	1	-0/+10
2022-04-28	clk: renesas: r9a07g043: Add OSTM clock and reset entries	Biju Das	1	-0/+9
2022-04-28	clk: renesas: r9a07g043: Add clock and reset entries for CANFD	Biju Das	1	-0/+5
2022-04-28	clk: renesas: r9a07g043: Add USB clocks/resets	Biju Das	1	-0/+12
2022-04-28	clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries	Biju Das	1	-0/+20
2022-04-28	clk: renesas: r9a07g043: Add I2C clocks/resets	Biju Das	1	-0/+12
2022-04-13	clk: renesas: r9a07g043: Add SDHI clock and reset entries	Biju Das	1	-0/+35
2022-04-13	clk: renesas: r9a07g043: Add GbEthernet clock/reset	Biju Das	1	-0/+10
2022-04-13	clk: renesas: r9a07g043: Add ethernet clock sources	Biju Das	1	-0/+13
2022-04-13	clk: renesas: r9a07g043: Add GPIO clock and reset entries	Biju Das	1	-0/+5
2022-04-13	clk: renesas: Add support for RZ/G2UL SoC	Biju Das	1	-0/+157