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path: root/drivers/clk/renesas/r8a77990-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2020-12-28clk: renesas: r8a77990: Add TMU clocksNiklas Söderlund1-0/+5
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht1-0/+1
2020-02-10clk: renesas: rcar-gen3: Add CCREE clocksGeert Uytterhoeven1-0/+2
2019-06-18clk: renesas: r8a77990: Add CMM clocksJacopo Mondi1-0/+2
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara1-9/+9
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi1-1/+1
2019-04-02clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara1-0/+1
2018-12-04clk: renesas: r8a77990: Correct parent clock of DUTakeshi Kihara1-2/+2
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven1-2/+2
2018-08-31clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven1-0/+1
2018-08-27clk: renesas: r8a77990: Correct RCLK handlingGeert Uytterhoeven1-2/+10
2018-05-09clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda1-0/+289