Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-09-04 | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 1 | -1/+1 |
2018-09-29 | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 1 | -4/+1 |
2018-04-16 | clk: renesas: r8a7794: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
2018-02-20 | clk: renesas: r8a7794: Add rwdt clock | Fabrizio Castro | 1 | -0/+2 |
2017-05-24 | clk: renesas: r8a7794: Add new CPG/MSSR driver | Geert Uytterhoeven | 1 | -0/+255 |