| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-08-29 | clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates | Sergio Paracuellos | 1 | -8/+1 |
| 2021-04-13 | clk: ralink: add clock driver for mt7621 SoC | Sergio Paracuellos | 3 | -0/+508 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |