starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-06-16	clk: mediatek: reset: Add new register reset function with device	Rex-BC Chen	1	-2/+2
2022-06-16	clk: mediatek: reset: Support nonsequence base offsets of reset registers	Rex-BC Chen	1	-4/+7
2022-06-16	clk: mediatek: reset: Revise structure to control reset register	Rex-BC Chen	1	-2/+17
2022-06-16	clk: mediatek: reset: Merge and revise reset register function	Rex-BC Chen	1	-2/+2
2022-05-20	clk: mediatek: Replace 'struct clk' with 'struct clk_hw'	Chen-Yu Tsai	1	-12/+14
2022-05-19	clk: mediatek: use en_mask as a pure div_en_mask	Chun-Jie Chen	1	-4/+4
2022-02-17	clk: mediatek: pll: Split definitions into separate header file	Chen-Yu Tsai	1	-2/+3
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	1	-9/+1
2019-02-25	clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel	chunhui dai	1	-2/+2
2018-08-31	clk: mediatek: remove unused array audio_parents	Colin Ian King	1	-5/+0
2018-05-16	clk: mediatek: correct the clocks for MT2701 HDMI PHY module	Ryder Lee	1	-2/+6
2018-03-19	clk: mediatek: fix PWM clock source by adding a fixed-factor clock	Sean Wang	1	-7/+8
2017-11-02	clk: mediatek: mark mtk_infrasys_init_early __init	Arnd Bergmann	1	-1/+1
2017-06-20	clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs	Sean Wang	1	-0/+8
2016-11-09	reset: mediatek: Add MT2701 reset driver	Shunli Wang	1	-2/+10
2016-11-09	clk: mediatek: Add MT2701 clock support	Shunli Wang	1	-0/+1027