index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
mediatek
/
clk-gate.h
Age
Commit message (
Expand
)
Author
Files
Lines
2022-05-20
clk: mediatek: Replace 'struct clk' with 'struct clk_hw'
Chen-Yu Tsai
1
-4
/
+4
2022-02-17
clk: mediatek: gate: Clean up included headers
Chen-Yu Tsai
1
-3
/
+7
2022-02-17
clk: mediatek: gate: Implement unregister API
Chen-Yu Tsai
1
-0
/
+3
2022-02-17
clk: mediatek: gate: Internalize clk implementation
Chen-Yu Tsai
1
-29
/
+2
2022-02-17
clk: mediatek: gate: Consolidate gate type clk related code
Chen-Yu Tsai
1
-0
/
+25
2019-09-17
clk: mediatek: Register clock gate with device
Weiyi Lu
1
-1
/
+2
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Thomas Gleixner
1
-9
/
+1
2019-04-11
clk: mediatek: Add MT8183 clock support
Weiyi Lu
1
-0
/
+14
2019-02-26
clk: mediatek: Add flags to mtk_gate
Jasper Mattsson
1
-1
/
+2
2016-11-09
clk: mediatek: Add MT2701 clock support
Shunli Wang
1
-0
/
+2
2016-01-29
clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
Geliang Tang
1
-1
/
+1
2015-07-20
clk: mediatek: Properly include clk.h
Stephen Boyd
1
-1
/
+2
2015-05-06
clk: mediatek: Add initial common clock support for Mediatek SoCs.
James Liao
1
-0
/
+49