index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
hisilicon
/
crg-hi3798cv200.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+1
2023-03-29
clk: hisilicon: Convert to platform remove callback returning void
Uwe Kleine-König
1
-3
/
+2
2019-05-21
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
Thomas Gleixner
1
-13
/
+1
2018-05-16
clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
Jianguo Sun
1
-0
/
+17
2018-03-12
clk: hi3798cv200: add emmc sample and drive clock
tianshuliang
1
-0
/
+20
2018-02-27
clk: hi3798cv200: add COMBPHY0 clock support
Jianguo Sun
1
-4
/
+11
2018-02-27
clk: hi3798cv200: fix define indentation
Shawn Guo
1
-24
/
+24
2018-02-27
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
Shawn Guo
1
-0
/
+2
2018-02-27
clk: hi3798cv200: correct IR clock parent
Younian Wang
1
-1
/
+1
2018-02-27
clk: hi3798cv200: fix unregister call sequence in error path
Shawn Guo
1
-7
/
+6
2017-11-14
clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
Shawn Guo
1
-1
/
+11
2017-06-21
clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
Jiancheng Xue
1
-0
/
+21
2016-11-12
clk: hisilicon: add CRG driver for Hi3798CV200 SoC
Jiancheng Xue
1
-0
/
+337