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path: root/drivers/clk/hisilicon/clk.h
AgeCommit message (Expand)AuthorFilesLines
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1Thomas Gleixner1-15/+1
2018-03-12clk: hisilicon: add hisi phase clock supporttianshuliang1-0/+19
2016-06-30clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue1-0/+21
2016-06-30clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue1-5/+5
2016-06-30clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue1-0/+3
2016-05-06clk: hisilicon: export some hisilicon APIs to modulesJiancheng Xue1-7/+7
2015-06-05clk: make several parent names constUwe Kleine-König1-1/+1
2015-06-04clk: hi6220: Clock driver support for Hisilicon hi6220 SoCBintian Wang1-0/+17
2015-06-03clk: hisilicon: Remove __init for marking function prototypesBintian Wang1-11/+11
2014-05-12clk: hisi: add hisi_clk_register_gateZhangfei Gao1-0/+2
2014-05-12clk: hisi: use clk_register_mux_table in hisi_clk_register_muxZhangfei Gao1-0/+1
2014-03-19clk: hisi: remove static variableHaojian Zhuang1-6/+11
2013-12-04clk: hisilicon: add common clock supportHaojian Zhuang1-0/+103
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