| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 1 | -0/+1 |
| 2017-05-21 | x86/mce: Convert threshold_bank.cpus from atomic_t to refcount_t | Elena Reshetova | 1 | -1/+2 |
| 2016-11-16 | x86/amd_nb: Add SMN and Indirect Data Fabric access for AMD Fam17h | Yazen Ghannam | 1 | -0/+5 |
| 2016-11-16 | x86/amd_nb: Make amd_northbridges internal to amd_nb.c | Yazen Ghannam | 1 | -15/+3 |
| 2016-03-08 | x86/mce/AMD: Document some functionality | Aravind Gopalakrishnan | 1 | -9/+17 |
| 2015-10-21 | x86/amd_nb, EDAC: Rename amd_get_node_id() | Aravind Gopalakrishnan | 1 | -1/+1 |
| 2015-05-06 | x86/gart: Check for GART support before accessing GART registers | Aravind Gopalakrishnan | 1 | -0/+11 |
| 2014-01-25 | x86/AMD/NB: Fix amd_set_subcaches() parameter type | Dan Carpenter | 1 | -1/+1 |
| 2013-01-10 | x86, AMD, NB: Add multi-domain support | Daniel J Blueman | 1 | -0/+17 |
| 2012-06-07 | x86, MCE, AMD: Move shared bank to node descriptor | Borislav Petkov | 1 | -0/+21 |
| 2012-01-07 | x86/PCI: amd: factor out MMCONFIG discovery | Bjorn Helgaas | 1 | -0/+2 |
| 2011-09-12 | x86: cache_info: Kill the atomic allocation in amd_init_l3_cache() | Thomas Gleixner | 1 | -0/+6 |
| 2011-05-02 | x86, NUMA: trivial cleanups | Tejun Heo | 1 | -1/+0 |
| 2011-03-16 | Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kern... | Linus Torvalds | 1 | -6/+6 |
| 2011-03-03 | x86, amd-nb: Misc cleanliness fixes | Borislav Petkov | 1 | -6/+6 |
| 2011-02-16 | x86-64, NUMA: Unify emulated distance mapping | Tejun Heo | 1 | -4/+0 |
| 2011-02-16 | x86-64, NUMA: Kill {acpi|amd|dummy}_scan_nodes() | Tejun Heo | 1 | -1/+0 |
| 2011-02-16 | x86-64, NUMA: Kill {acpi|amd}_get_nodes() | Tejun Heo | 1 | -1/+0 |
| 2011-02-16 | x86-64, NUMA: Unify {acpi|amd}_{numa_init|scan_nodes}() arguments and return ... | Tejun Heo | 1 | -1/+1 |
| 2011-02-10 | x86: Adjust section placement in AMD northbridge related code | Jan Beulich | 1 | -1/+1 |
| 2011-02-07 | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs | Hans Rosenfeld | 1 | -0/+3 |
| 2011-01-26 | x86, amd: Extend AMD northbridge caching code to support "Link Control" devices | Hans Rosenfeld | 1 | -0/+1 |
| 2011-01-11 | x86: Use PCI method for enabling AMD extended config space before MSR method | Jan Beulich | 1 | -0/+7 |
| 2010-12-24 | x86, numa: Fix cpu to node mapping for sparse node ids | David Rientjes | 1 | -1/+1 |
| 2010-12-24 | x86, numa: Fake apicid and pxm mappings for NUMA emulation | David Rientjes | 1 | -0/+1 |
| 2010-12-24 | x86, numa: Avoid compiling NUMA emulation functions without CONFIG_NUMA_EMU | David Rientjes | 1 | -1/+4 |
| 2010-11-18 | x86, cacheinfo: Cleanup L3 cache index disable support | Hans Rosenfeld | 1 | -0/+1 |
| 2010-11-18 | x86, amd-nb: Cleanup AMD northbridge caching code | Hans Rosenfeld | 1 | -9/+25 |
| 2010-11-18 | x86, amd-nb: Complete the rename of AMD NB and related code | Hans Rosenfeld | 1 | -12/+12 |
| 2010-09-21 | x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB | Andreas Herrmann | 1 | -0/+39 |
