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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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arch
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riscv
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Author
Files
Lines
2018-11-02
RISC-V: refresh defconfig
Anup Patel
1
-8
/
+8
2018-11-01
Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...
Linus Torvalds
3
-7
/
+5
2018-10-31
lib: Remove umoddi3 and udivmoddi4
Palmer Dabbelt
1
-1
/
+0
2018-10-31
Move EM_RISCV into elf-em.h
Palmer Dabbelt
1
-3
/
+0
2018-10-31
RISC-V: properly determine hardware caps
Andreas Schwab
1
-3
/
+5
2018-10-31
Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"
Palmer Dabbelt
1
-1
/
+0
2018-10-31
mm: remove include/linux/bootmem.h
Mike Rapoport
1
-2
/
+1
2018-10-31
memblock: rename free_all_bootmem to memblock_free_all
Mike Rapoport
1
-1
/
+1
2018-10-31
mm: remove CONFIG_HAVE_MEMBLOCK
Mike Rapoport
1
-1
/
+0
2018-10-31
mm: remove CONFIG_NO_BOOTMEM
Mike Rapoport
1
-1
/
+0
2018-10-31
treewide: remove current_text_addr
Nick Desaulniers
1
-6
/
+0
2018-10-26
Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...
Linus Torvalds
27
-238
/
+679
2018-10-25
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...
Linus Torvalds
1
-0
/
+1
2018-10-24
Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds
2
-24
/
+1
2018-10-23
RISC-V: SMP cleanup and new features
Palmer Dabbelt
10
-62
/
+245
2018-10-23
RISC-V: Fix some RV32 bugs and build failures
Palmer Dabbelt
4
-2
/
+7
2018-10-23
riscv: Add support to no-FPU systems
Palmer Dabbelt
9
-127
/
+196
2018-10-23
RISC-V: Cosmetic menuconfig changes
Nick Kossifidis
2
-36
/
+39
2018-10-23
riscv: move GCC version check for ARCH_SUPPORTS_INT128 to Kconfig
Masahiro Yamada
2
-2
/
+1
2018-10-23
RISC-V: remove the unused return_to_handler export
Christoph Hellwig
1
-1
/
+0
2018-10-23
RISC-V: Add futex support.
Jim Wilson
3
-1
/
+129
2018-10-23
RISC-V: Add FP register ptrace support for gdb.
Jim Wilson
2
-0
/
+55
2018-10-23
RISC-V: Mask out the F extension on systems without D
Palmer Dabbelt
1
-0
/
+7
2018-10-23
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
Palmer Dabbelt
1
-7
/
+0
2018-10-23
RISC-V: Show IPI stats
Anup Patel
3
-7
/
+49
2018-10-23
RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo
Anup Patel
1
-4
/
+6
2018-10-23
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
6
-25
/
+58
2018-10-23
RISC-V: Add logical CPU indexing for RISC-V
Atish Patra
3
-1
/
+46
2018-10-23
RISC-V: Use WRITE_ONCE instead of direct access
Atish Patra
1
-2
/
+3
2018-10-23
RISC-V: Use mmgrab()
Palmer Dabbelt
1
-1
/
+2
2018-10-23
RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
Palmer Dabbelt
1
-4
/
+5
2018-10-23
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
3
-4
/
+7
2018-10-23
RISC-V: Provide a cleaner raw_smp_processor_id()
Palmer Dabbelt
1
-10
/
+4
2018-10-23
RISC-V: Disable preemption before enabling interrupts
Atish Patra
1
-1
/
+5
2018-10-23
RISC-V: Comment on the TLB flush in smp_callin()
Palmer Dabbelt
1
-0
/
+4
2018-10-23
RISC-V: Filter ISA and MMU values in cpuinfo
Palmer Dabbelt
1
-7
/
+61
2018-10-23
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
Palmer Dabbelt
1
-7
/
+0
2018-10-23
RISC-V: No need to pass scause as arg to do_IRQ()
Anup Patel
2
-3
/
+2
2018-10-23
RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap
Vincent Chen
1
-1
/
+1
2018-10-23
RISC-V: Select GENERIC_LIB_UMODDI3 on RV32
Zong Li
1
-0
/
+1
2018-10-23
RISC-V: Use swiotlb on RV64 only
Zong Li
1
-0
/
+3
2018-10-23
RISC-V: Build tishift only on 64-bit
Zong Li
1
-1
/
+2
2018-10-23
Auto-detect whether a FPU exists
Alan Kao
4
-7
/
+19
2018-10-23
Allow to disable FPU support
Alan Kao
6
-3
/
+29
2018-10-23
Cleanup ISA string setting
Alan Kao
1
-11
/
+8
2018-10-23
Refactor FPU code in signal setup/return procedures
Alan Kao
1
-27
/
+41
2018-10-23
Extract FPU context operations from entry.S
Alan Kao
3
-87
/
+107
2018-10-03
signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZE
Eric W. Biederman
2
-24
/
+1
2018-10-02
RISCV: Fix end PFN for low memory
Atish Patra
1
-1
/
+1
2018-09-24
RISC-V: include linux/ftrace.h in asm-prototypes.h
James Cowgill
1
-0
/
+7
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