index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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riscv
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mm
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2019-05-19
Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
5
-6
/
+310
2019-05-17
riscv: fix locking violation in page fault handler
Andreas Schwab
1
-1
/
+2
2019-05-17
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
Yash Shah
2
-0
/
+176
2019-05-17
riscv: move switch_mm to its own file
Gary Guo
2
-0
/
+70
2019-05-17
riscv: move flush_icache_{all,mm} to cacheflush.c
Gary Guo
1
-0
/
+61
2019-05-17
RISC-V: Access CSRs using CSR numbers
Anup Patel
1
-5
/
+1
2019-05-14
riscv: switch over to generic free_initmem()
Mike Rapoport
1
-5
/
+0
2019-04-10
RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems
Anup Patel
1
-0
/
+8
2019-03-27
RISC-V: Always compile mm/init.c with cmodel=medany and notrace
Anup Patel
2
-0
/
+34
2019-02-21
RISC-V: Free-up initrd in free_initrd_mem()
Anup Patel
1
-1
/
+2
2019-02-21
RISC-V: Implement compile-time fixed mappings
Anup Patel
1
-0
/
+34
2019-02-21
RISC-V: Move setup_vm() to mm/init.c
Anup Patel
1
-0
/
+49
2019-02-21
RISC-V: Move setup_bootmem() to mm/init.c
Anup Patel
1
-0
/
+70
2019-01-24
riscv: fixup max_low_pfn with PFN_DOWN.
Guo Ren
1
-1
/
+2
2018-10-31
mm: remove include/linux/bootmem.h
Mike Rapoport
1
-2
/
+1
2018-10-31
memblock: rename free_all_bootmem to memblock_free_all
Mike Rapoport
1
-1
/
+1
2018-10-23
RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap
Vincent Chen
1
-1
/
+1
2018-08-18
mm: convert return type of handle_mm_fault() caller to vm_fault_t
Souptick Joarder
1
-1
/
+2
2018-07-04
RISC-V: Add conditional macro for zone of DMA32
Zong Li
1
-0
/
+2
2018-02-07
Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm...
Linus Torvalds
2
-6
/
+10
2018-02-01
Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds
1
-1
/
+0
2018-01-31
riscv: rename sptbr to satp
Christoph Hellwig
1
-0
/
+4
2018-01-31
riscv: don't read back satp in paging_init
Christoph Hellwig
1
-2
/
+0
2018-01-31
riscv: add ZONE_DMA32
Christoph Hellwig
1
-4
/
+6
2018-01-08
riscv: rename SR_* constants to match the spec
Christoph Hellwig
1
-1
/
+1
2017-12-05
riscv: use linux/uaccess.h, not asm/uaccess.h...
Al Viro
1
-1
/
+0
2017-12-02
RISC-V: Fixes for clean allmodconfig build
Palmer Dabbelt
1
-1
/
+1
2017-11-30
RISC-V: Flush I$ when making a dirty page executable
Andrew Waterman
2
-0
/
+24
2017-11-30
RISC-V: io.h: type fixes for warnings
Olof Johansson
1
-1
/
+1
2017-09-27
RISC-V: Build Infrastructure
Palmer Dabbelt
1
-0
/
+4
2017-09-27
RISC-V: Paging and MMU
Palmer Dabbelt
1
-0
/
+282
2017-09-27
RISC-V: Device, timer, IRQs, and the SBI
Palmer Dabbelt
1
-0
/
+92
2017-09-27
RISC-V: ELF and module implementation
Palmer Dabbelt
1
-0
/
+37
2017-09-27
RISC-V: Init and Halt Code
Palmer Dabbelt
1
-0
/
+70