starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-04-29	riscv: mm: Combine the SMP and UP TLB flush code	Samuel Holland	1	-4/+1
2023-12-20	riscv: mm: Only compile pgtable.c if MMU	Alexandre Ghiti	1	-2/+1
2023-11-07	riscv: split cache ops out of dma-noncoherent.c	Christoph Hellwig	1	-0/+1
2023-06-14	riscv: mm: stub extable related functions/macros for !MMU	Jisheng Zhang	1	-2/+1
2023-04-19	riscv: Introduce CONFIG_RELOCATABLE	Alexandre Ghiti	1	-0/+4
2022-12-09	Merge patch series "Add PMEM support for RISC-V"	Palmer Dabbelt	1	-0/+1
2022-12-09	RISC-V: Implement arch specific PMEM APIs	Anup Patel	1	-0/+1
2022-10-29	riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT	Liu Shixin	1	-0/+1
2022-07-29	riscv: Add support for non-coherent devices using zicbom extension	Heiko Stuebner	1	-0/+1
2022-03-04	riscv: Fix config KASAN && DEBUG_VIRTUAL	Alexandre Ghiti	1	-0/+3
2021-01-15	riscv: Fixup patch_text panic in ftrace	Guo Ren	1	-0/+1
2021-01-15	riscv: Fixup wrong ftrace remove cflag	Guo Ren	1	-1/+1
2020-07-30	riscv: Allow building with kcov coverage	Tobias Klauser	1	-0/+2
2020-03-26	riscv: Add support to dump the kernel page tables	Zong Li	1	-0/+1
2020-03-26	riscv: add ARCH_HAS_SET_MEMORY support	Zong Li	1	-1/+1
2020-01-23	riscv: mm: add support for CONFIG_DEBUG_VIRTUAL	Zong Li	1	-0/+2
2020-01-23	riscv: Add KASAN support	Nick Hu	1	-0/+6
2019-12-20	riscv: move sifive_l2_cache.c to drivers/soc	Christoph Hellwig	1	-1/+0
2019-11-28	Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap	Linus Torvalds	1	-1/+1
2019-11-18	riscv: add nommu support	Christoph Hellwig	1	-2/+1
2019-11-11	riscv: use the generic ioremap code	Christoph Hellwig	1	-1/+0
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	1	-0/+3
2019-07-04	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti	1	-0/+2
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	1	-0/+1
2019-05-17	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah	1	-0/+1
2019-05-17	riscv: move switch_mm to its own file	Gary Guo	1	-0/+1
2019-03-27	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	Anup Patel	1	-0/+6
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-0/+1
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	1	-0/+4