starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-09-01	RISC-V: alternative: Remove feature_probe_func	Evan Green	1	-1/+0
2023-09-01	RISC-V: Probe for unaligned access speed	Evan Green	1	-0/+2
2023-07-05	risc-v: Fix order of IPI enablement vs RCU startup	Marc Zyngier	1	-2/+3
2023-06-23	Merge patch series "ISA string parser cleanups"	Palmer Dabbelt	1	-1/+1
2023-06-21	RISC-V: split early & late of_node to hartid mapping	Conor Dooley	1	-1/+1
2023-06-08	Merge patch series "riscv: Add vector ISA support"	Palmer Dabbelt	1	-0/+7
2023-06-08	riscv: Introduce riscv_v_vsize to record size of Vector context	Greentime Hu	1	-0/+7
2023-06-01	RISC-V: smpboot: Add ACPI support in setup_smp()	Sunil V L	1	-1/+71
2023-06-01	RISC-V: smpboot: Create wrapper setup_smp()	Sunil V L	1	-1/+6
2023-04-29	Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-0/+1
2023-04-19	RISC-V: hwprobe: Support probing of misaligned access performance	Evan Green	1	-0/+1
2023-04-08	RISC-V: Treat IPIs as normal Linux IRQs	Anup Patel	1	-3/+2
2023-01-25	riscv: Move call to init_cpu_topology() to later initialization stage	Ley Foon Tan	1	-1/+2
2022-08-16	riscv: topology: fix default topology reporting	Conor Dooley	1	-1/+2
2022-07-20	riscv: cpu: Add 64bit hartid support on RV64	Sunil V L	1	-4/+5
2022-05-12	riscv: move boot alternatives to after fill_hwcap	Heiko Stuebner	1	-2/+0
2022-05-12	riscv: integrate alternatives better into the main architecture	Heiko Stuebner	1	-2/+0
2022-01-20	RISC-V: Do not use cpumask data structure for hartid bitmap	Atish Patra	1	-1/+1
2021-05-12	sched/core: Initialize the idle task with preemption disabled	Valentin Schneider	1	-1/+0
2021-04-26	riscv: Introduce alternative mechanism to apply errata solution	Vincent Chen	1	-0/+4
2021-01-15	riscv: Add numa support for riscv64 platform	Atish Patra	1	-1/+11
2020-08-20	RISC-V: Remove CLINT related code from timer and arch	Anup Patel	1	-1/+0
2020-08-20	RISC-V: Add mechanism to provide custom IPI operations	Anup Patel	1	-2/+1
2020-08-05	RISC-V: Fix build warning for smpboot.c	Atish Patra	1	-1/+1
2020-07-30	RISC-V: Setup exception vector early	Atish Patra	1	-1/+1
2020-07-30	riscv: Fixup lockdep_assert_held with wrong param cpu_running	Zong Li	1	-1/+0
2020-06-30	RISC-V: Use a local variable instead of smp_processor_id()	Greentime Hu	1	-3/+4
2020-03-31	RISC-V: Add supported for ordered booting method using HSM	Atish Patra	1	-1/+1
2020-03-31	RISC-V: Add cpu_ops and modify default booting method	Atish Patra	1	-21/+30
2019-11-18	riscv: provide native clint access for M-mode	Christoph Hellwig	1	-0/+4
2019-10-28	riscv: for C functions called only from assembly, mark with __visible	Paul Walmsley	1	-1/+1
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+1
2019-10-28	riscv: add prototypes for assembly language functions from head.S	Paul Walmsley	1	-0/+2
2019-07-22	RISC-V: Parse cpu topology during boot.	Atish Patra	1	-0/+3
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	1	-9/+1
2019-05-17	RISC-V: Support nr_cpus command line option.	Atish Patra	1	-1/+9
2019-04-30	RISC-V: Implement nosmp commandline option.	Atish Patra	1	-1/+11
2019-03-04	RISC-V: Compare cpuid with NR_CPUS before mapping.	Atish Patra	1	-0/+5
2019-03-04	RISC-V: Do not wait indefinitely in __cpu_up	Atish Patra	1	-3/+12
2019-02-12	riscv: use for_each_of_cpu_node iterator	Johan Hovold	1	-2/+2
2019-01-23	RISC-V: fix bad use of of_node_put	Andreas Schwab	1	-5/+1
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	1	-1/+5
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-9/+16
2018-10-23	RISC-V: Use WRITE_ONCE instead of direct access	Atish Patra	1	-2/+3
2018-10-23	RISC-V: Use mmgrab()	Palmer Dabbelt	1	-1/+2
2018-10-23	RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu	Palmer Dabbelt	1	-4/+5
2018-10-23	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid	Palmer Dabbelt	1	-1/+1
2018-10-23	RISC-V: Disable preemption before enabling interrupts	Atish Patra	1	-1/+5
2018-10-23	RISC-V: Comment on the TLB flush in smp_callin()	Palmer Dabbelt	1	-0/+4
2018-08-13	clocksource: new RISC-V SBI timer driver	Palmer Dabbelt	1	-1/+0