starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-05-17	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-49/+0
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-1/+1
2019-05-17	RISC-V: Fix minor checkpatch issues.	Atish Patra	1	-2/+2
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra	1	-0/+6
2019-03-04	RISC-V: Fixmap support and MM cleanups	Palmer Dabbelt	1	-1/+1
2019-03-04	RISC-V: Allow hartid-to-cpuid function to fail.	Atish Patra	1	-1/+0
2019-03-04	RISC-V: Move cpuid to hartid mapping to SMP.	Atish Patra	1	-0/+9
2019-01-07	riscv: don't stop itself in smp_send_stop	Andreas Schwab	1	-7/+36
2018-10-23	RISC-V: Show IPI stats	Anup Patel	1	-7/+32
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-9/+15
2018-10-23	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra	1	-0/+19
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig	1	-4/+2
2017-12-02	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt	1	-0/+7
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-0/+48
2017-11-30	RISC-V: Provide stub of setup_profiling_timer()	Olof Johansson	1	-0/+7
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+110