starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-11-28	RISC-V: drop error print from riscv_hartid_to_cpuid()	Conor Dooley	1	-1/+0
2022-11-30	riscv: kexec: Fixup crash_smp_send_stop without multi cores	Guo Ren	1	-2/+95
2022-08-07	Merge tag 'mm-nonmm-stable-2022-08-06-2' of git://git.kernel.org/pub/scm/linu...	Linus Torvalds	1	-6/+0
2022-07-30	profile: setup_profiling_timer() is moslty not implemented	Ben Dooks	1	-6/+0
2022-07-20	riscv: smp: Add 64bit hartid support on RV64	Sunil V L	1	-2/+2
2022-01-09	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	Sean Christopherson	1	-10/+0
2021-10-26	irq: riscv: perform irqentry in entry code	Mark Rutland	1	-8/+1
2021-05-01	RISC-V: Fix error code returned by riscv_hartid_to_cpuid()	Anup Patel	1	-1/+1
2021-04-26	riscv: Constify sbi_ipi_ops	Jisheng Zhang	1	-2/+2
2021-04-26	riscv: Mark some global variables __ro_after_init	Jisheng Zhang	1	-2/+2
2021-03-17	riscv: Enable generic clockevent broadcast	Guo Ren	1	-0/+16
2020-08-20	RISC-V: Remove CLINT related code from timer and arch	Anup Patel	1	-1/+0
2020-08-20	RISC-V: Add mechanism to provide custom IPI operations	Anup Patel	1	-19/+24
2020-07-30	riscv: Support irq_work via self IPIs	Greentime Hu	1	-0/+15
2020-06-10	RISC-V: self-contained IPI handling routine	Anup Patel	1	-2/+9
2020-05-05	RISC-V: Export riscv_cpuid_to_hartid_mask() API	Anup Patel	1	-0/+2
2020-03-19	riscv: fix the IPI missing issue in nommu mode	Greentime Hu	1	-1/+1
2019-11-18	riscv: provide native clint access for M-mode	Christoph Hellwig	1	-3/+13
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-1/+1
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+2
2019-09-20	RISC-V: Export kernel symbols for kvm	Atish Patra	1	-0/+1
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	1	-0/+1
2019-09-05	riscv: optimize send_ipi_single	Christoph Hellwig	1	-1/+7
2019-09-05	riscv: cleanup send_ipi_mask	Christoph Hellwig	1	-9/+7
2019-09-05	riscv: refactor the IPI code	Christoph Hellwig	1	-24/+31
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner	1	-12/+1
2019-05-17	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-49/+0
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-1/+1
2019-05-17	RISC-V: Fix minor checkpatch issues.	Atish Patra	1	-2/+2
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra	1	-0/+6
2019-03-04	RISC-V: Fixmap support and MM cleanups	Palmer Dabbelt	1	-1/+1
2019-03-04	RISC-V: Allow hartid-to-cpuid function to fail.	Atish Patra	1	-1/+0
2019-03-04	RISC-V: Move cpuid to hartid mapping to SMP.	Atish Patra	1	-0/+9
2019-01-07	riscv: don't stop itself in smp_send_stop	Andreas Schwab	1	-7/+36
2018-10-23	RISC-V: Show IPI stats	Anup Patel	1	-7/+32
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-9/+15
2018-10-23	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra	1	-0/+19
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig	1	-4/+2
2017-12-02	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt	1	-0/+7
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-0/+48
2017-11-30	RISC-V: Provide stub of setup_profiling_timer()	Olof Johansson	1	-0/+7
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+110