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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
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riscv
/
kernel
/
sbi.c
Age
Commit message (
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Author
Files
Lines
2024-09-03
riscv: Fix RISCV_ALTERNATIVE_EARLY
Alexandre Ghiti
1
-63
/
+0
2024-07-10
riscv: Improve sbi_ecall() code generation by reordering arguments
Alexandre Ghiti
1
-5
/
+5
2024-07-10
riscv: Add tracepoints for SBI calls and returns
Samuel Holland
1
-0
/
+7
2024-01-10
RISC-V: Add SBI debug console helper routines
Anup Patel
1
-0
/
+66
2023-11-06
riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
Alexandre Ghiti
1
-22
/
+10
2023-04-29
RISC-V: Align SBI probe implementation with spec
Andrew Jones
1
-9
/
+8
2023-04-08
RISC-V: Treat IPIs as normal Linux IRQs
Anup Patel
1
-90
/
+16
2023-04-08
RISC-V: Clear SIP bit only when using SBI IPI operations
Anup Patel
1
-1
/
+7
2022-12-07
RISC-V: Export sbi_get_mvendorid() and friends
Anup Patel
1
-0
/
+3
2022-02-14
RISC-V: Fix IPI/RFENCE hmask on non-monotonic hartid ordering
Geert Uytterhoeven
1
-18
/
+39
2022-02-14
RISC-V: Fix handling of empty cpu masks
Geert Uytterhoeven
1
-4
/
+4
2022-02-14
RISC-V: Fix hartid mask handling for hartid 31 and up
Geert Uytterhoeven
1
-3
/
+4
2022-01-20
RISC-V: Do not use cpumask data structure for hartid bitmap
Atish Patra
1
-83
/
+106
2022-01-11
RISC-V: Use SBI SRST extension when available
Anup Patel
1
-0
/
+35
2021-05-06
Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...
Linus Torvalds
1
-8
/
+23
2021-04-26
riscv: Constify sbi_ipi_ops
Jisheng Zhang
1
-1
/
+1
2021-04-26
riscv: Mark some global variables __ro_after_init
Jisheng Zhang
1
-4
/
+4
2021-04-26
riscv: Add 3 SBI wrapper functions to get cpu manufacturer information
Vincent Chen
1
-0
/
+15
2021-03-30
RISC-V: Don't print SBI version for all detected extensions
Anup Patel
1
-3
/
+3
2021-03-10
riscv: sbi: Fix comment of __sbi_set_timer_v01
Nanyong Sun
1
-1
/
+1
2021-02-23
RISC-V: Add a non-void return for sbi v02 functions
Atish Patra
1
-16
/
+16
2021-01-08
riscv: Cleanup sbi function stubs when RISCV_SBI disabled
Kefeng Wang
1
-3
/
+1
2020-08-20
RISC-V: Add mechanism to provide custom IPI operations
Anup Patel
1
-0
/
+14
2020-04-22
riscv: sbi: Fix undefined reference to sbi_shutdown
Kefeng Wang
1
-5
/
+8
2020-04-22
riscv: sbi: Correct sbi_shutdown() and sbi_clear_ipi() export
Kefeng Wang
1
-2
/
+2
2020-03-31
RISC-V: Export SBI error to linux error mapping function
Atish Patra
1
-1
/
+2
2020-03-31
RISC-V: Implement new SBI v0.2 extensions
Atish Patra
1
-4
/
+249
2020-03-31
RISC-V: Introduce a new config for SBI v0.1
Atish Patra
1
-23
/
+109
2020-03-31
RISC-V: Add basic support for SBI v0.2
Atish Patra
1
-2
/
+241
2019-11-14
riscv: cleanup the default power off implementation
Christoph Hellwig
1
-0
/
+17