starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-09-20	arch/riscv: disable excess harts before picking main boot hart	Xiang Wang	1	-3/+5
2019-09-17	Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-1/+1
2019-09-14	riscv: modify the Image header to improve compatibility with the ARM64 header	Paul Walmsley	1	-2/+2
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	1	-1/+1
2019-07-11	RISC-V: Add an Image header that boot loader can parse.	Atish Patra	1	-0/+32
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel	1	-8/+9
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-17	RISC-V: Avoid using invalid intermediate translations	Palmer Dabbelt	1	-2/+10
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-8/+8
2019-04-26	riscv: cleanup the parse_dtb calling conventions	Christoph Hellwig	1	-2/+1
2019-04-26	riscv: simplify the stack pointer setup in head.S	Christoph Hellwig	1	-4/+1
2019-04-26	riscv: clear all pending interrupts when booting	Christoph Hellwig	1	-1/+2
2018-11-20	RISC-V: Build flat and compressed kernel images	Anup Patel	1	-0/+10
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-1/+3
2018-08-13	RISC-V: Add the directive for alignment of stvec's value	Zong Li	1	-0/+2
2018-02-20	Rename sbi_save to parse_dtb to improve code readability	Michael Clark	1	-1/+1
2018-01-31	riscv: rename sptbr to satp	Christoph Hellwig	1	-3/+3
2017-11-30	RISC-V: move empty_zero_page definition to C and export it	Olof Johansson	1	-3/+0
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+157