| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-05-23 | riscv: typo in comment for get_f64_reg | Xingyou Chen | 1 | -1/+1 |
| 2023-11-06 | riscv: Use SYM_*() assembly macros instead of deprecated ones | Clément Léger | 1 | -4/+4 |
| 2023-11-01 | riscv: add floating point insn support to misaligned access emulation | Clément Léger | 1 | -0/+121 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | 1 | -4/+4 |
| 2019-08-30 | riscv: Using CSR numbers to access CSRs | Bin Meng | 1 | -4/+4 |
| 2018-10-23 | Extract FPU context operations from entry.S | Alan Kao | 1 | -0/+106 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |