starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-12-10	RISC-V: Ensure Zicbom has a valid block size	Andrew Jones	1	-0/+13
2022-12-10	RISC-V: Introduce riscv_isa_extension_check	Andrew Jones	1	-3/+11
2022-12-10	RISC-V: Improve use of isa2hwcap[]	Andrew Jones	1	-9/+11
2022-10-14	Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-23/+16
2022-10-13	Merge patch series "Some style cleanups for recent extension additions"	Palmer Dabbelt	1	-23/+16
2022-10-13	riscv: use BIT() marco for cpufeature probing	Heiko Stuebner	1	-2/+2
2022-10-13	riscv: drop some idefs from CMO initialization	Heiko Stuebner	1	-13/+9
2022-10-13	riscv: cleanup svpbmt cpufeature probing	Heiko Stuebner	1	-8/+5
2022-10-02	RISC-V: Probe Svinval extension form ISA string	Mayuresh Chitale	1	-0/+1
2022-08-17	riscv: Ensure isa-ext static keys are writable	Andrew Jones	1	-1/+1
2022-08-12	RISC-V: Add Sstc extension support	Palmer Dabbelt	1	-0/+1
2022-08-12	RISC-V: Enable sstc extension parsing from DT	Atish Patra	1	-0/+1
2022-08-11	arch/riscv: add Zihintpause support	Dao Lu	1	-0/+1
2022-08-11	riscv: implement Zicbom-based CMO instructions + the t-head variant	Palmer Dabbelt	1	-0/+24
2022-07-29	riscv: Add support for non-coherent devices using zicbom extension	Heiko Stuebner	1	-0/+24
2022-07-20	RISC-V: Support for 64bit hartid on RV64 platforms	Palmer Dabbelt	1	-2/+4
2022-07-20	riscv: cpu: Add 64bit hartid support on RV64	Sunil V L	1	-2/+4
2022-06-17	RISC-V: Some Svpbmt fixes and cleanups	Palmer Dabbelt	1	-26/+11
2022-06-17	riscv: remove usage of function-pointers from cpufeatures and t-head errata	Heiko Stuebner	1	-22/+10
2022-06-17	riscv: drop cpufeature_apply_feature tracking variable	Heiko Stuebner	1	-4/+1
2022-06-16	riscv: switch has_fpu() to the unified static key mechanism	Jisheng Zhang	1	-7/+0
2022-06-16	riscv: introduce unified static key mechanism for ISA extensions	Jisheng Zhang	1	-0/+7
2022-06-05	Merge tag 'bitmap-for-5.19-rc1' of https://github.com/norov/linux	Linus Torvalds	1	-4/+3
2022-06-03	risc-v: replace bitmap_weight with bitmap_empty in riscv_fill_hwcap()	Yury Norov	1	-4/+3
2022-05-12	riscv: add memory-type errata for T-Head	Heiko Stuebner	1	-1/+6
2022-05-12	riscv: add RISC-V Svpbmt extension support	Heiko Stuebner	1	-1/+74
2022-03-22	RISC-V: Add sscofpmf extension support	Atish Patra	1	-0/+2
2022-03-17	RISC-V: Do no continue isa string parsing without correct XLEN	Atish Patra	1	-0/+5
2022-03-17	RISC-V: Implement multi-letter ISA extension probing framework	Atish Patra	1	-6/+16
2022-03-17	RISC-V: Extract multi-letter extension names from "riscv, isa"	Tsukasa OI	1	-8/+27
2022-03-17	RISC-V: Minimal parser for "riscv, isa" strings	Tsukasa OI	1	-11/+61
2022-03-17	RISC-V: Correctly print supported extensions	Tsukasa OI	1	-3/+5
2021-05-29	riscv: Add __init section marker to some functions again	Jisheng Zhang	1	-1/+1
2021-05-26	riscv: Turn has_fpu into a static key if FPU=y	Jisheng Zhang	1	-2/+2
2020-05-05	RISC-V: Add bitmap reprensenting ISA features common across CPUs	Anup Patel	1	-3/+80
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+1
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner	1	-12/+1
2019-03-04	RISC-V: Assign hwcap as per comman capabilities.	Atish Patra	1	-19/+22
2019-02-12	riscv: use for_each_of_cpu_node iterator	Johan Hovold	1	-2/+3
2019-02-12	riscv: add missing newlines to printk messages	Johan Hovold	1	-4/+4
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	1	-0/+2
2018-10-31	RISC-V: properly determine hardware caps	Andreas Schwab	1	-3/+5
2018-10-23	riscv: Add support to no-FPU systems	Palmer Dabbelt	1	-0/+8
2018-10-23	RISC-V: Mask out the F extension on systems without D	Palmer Dabbelt	1	-0/+7
2018-10-23	Auto-detect whether a FPU exists	Alan Kao	1	-0/+8
2017-09-27	RISC-V: User-facing API	Palmer Dabbelt	1	-0/+61