starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-09-16	riscv: cacheinfo: Add back init_cache_level() function	Steffen Persvold	1	-0/+5
2024-07-24	riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT	Yunhui Cui	1	-0/+22
2024-07-24	riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init()	Yunhui Cui	1	-7/+6
2023-04-29	Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-51/+15
2023-04-14	riscv: cacheinfo: Adjust includes to remove of_device.h	Rob Herring	1	-1/+0
2023-04-12	Revert "riscv: Set more data to cacheinfo"	Song Shuai	1	-51/+15
2023-01-18	arch_topology: Build cacheinfo from primary CPU	Pierre Gondois	1	-5/+0
2023-01-18	cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation	Pierre Gondois	1	-38/+1
2021-09-01	drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()	Thomas Gleixner	1	-5/+2
2021-01-13	riscv: cacheinfo: Fix using smp_processor_id() in preemptible	Kefeng Wang	1	-1/+10
2020-09-16	riscv: Add cache information in AUX vector	Zong Li	1	-1/+31
2020-09-16	riscv: Set more data to cacheinfo	Zong Li	1	-15/+51
2020-05-21	riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure	Yash Shah	1	-0/+17
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	1	-0/+11
2018-10-23	RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}	Palmer Dabbelt	1	-7/+0
2018-05-17	drivers: base: cacheinfo: setup DT cache properties early	Jeremy Linton	1	-1/+0
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+105