starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-11-18	riscv: add nommu support	Christoph Hellwig	1	-3/+9
2019-10-14	riscv: tlbflush: remove confusing comment on local_flush_tlb_all()	Paul Walmsley	1	-4/+0
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	1	-30/+7
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	1	-1/+0
2019-08-14	riscv: fix flush_tlb_range() end address for flush_tlb_page()	Paul Walmsley	1	-2/+9
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-3/+13
2018-06-07	riscv: use NULL instead of a plain 0	Luc Van Oostenryck	1	-1/+1
2018-01-31	RISC-V: Limit the scope of TLB shootdowns	Andrew Waterman	1	-8/+12
2018-01-08	riscv: remove CONFIG_MMU ifdefs	Christoph Hellwig	1	-4/+0
2017-12-02	RISC-V: User-Visible Changes	Palmer Dabbelt	1	-0/+2
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-0/+2
2017-11-29	RISC-V: `sfence.vma` orderes the instruction cache	Palmer Dabbelt	1	-1/+4
2017-09-27	RISC-V: Atomic and Locking Code	Palmer Dabbelt	1	-0/+64