Age | Commit message (Expand) | Author | Files | Lines |
2021-03-10 | riscv: time: Fix no prototype for time_init | Nanyong Sun | 1 | -0/+2 |
2020-12-11 | RISC-V: Define get_cycles64() regardless of M-mode | Palmer Dabbelt | 1 | -2/+2 |
2020-09-30 | RISC-V: Check clint_time_val before use | Anup Patel | 1 | -0/+13 |
2020-09-19 | RISC-V: Resurrect the MMIO timer implementation for M-mode systems | Palmer Dabbelt | 1 | -0/+27 |
2020-08-20 | RISC-V: Remove CLINT related code from timer and arch | Anup Patel | 1 | -21/+7 |
2019-11-14 | riscv: add support for MMIO access to the timer registers | Christoph Hellwig | 1 | -2/+17 |
2019-09-05 | riscv: don't use the rdtime(h) pseudo-instructions | Christoph Hellwig | 1 | -23/+21 |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
2017-11-30 | RISC-V: Use define for get_cycles like other architectures | Olof Johansson | 1 | -1/+2 |
2017-09-27 | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 1 | -0/+59 |