starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-05-05	RISC-V: Remove N-extension related defines	Anup Patel	1	-3/+0
2020-02-18	riscv: set pmp configuration if kernel is running in M-mode	Greentime Hu	1	-0/+12
2020-01-05	riscv: prefix IRQ_ macro names with an RV_ namespace	Paul Walmsley	1	-9/+9
2019-11-18	riscv: clear the instruction cache and all registers when booting	Christoph Hellwig	1	-0/+1
2019-11-18	riscv: read the hart ID from mhartid on boot	Damien Le Moal	1	-0/+1
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-10/+62
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-7/+25
2019-05-17	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	Anup Patel	1	-4/+17
2019-05-17	RISC-V: Use tabs to align macro values in asm/csr.h	Anup Patel	1	-38/+38
2018-08-13	RISC-V: add a definition for the SIE SEIE bit	Christoph Hellwig	1	-0/+1
2018-01-31	riscv: rename sptbr to satp	Christoph Hellwig	1	-7/+7
2018-01-08	riscv: rename SR_* constants to match the spec	Christoph Hellwig	1	-4/+4
2017-09-27	RISC-V: Generic library routines and assembly	Palmer Dabbelt	1	-0/+132