index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
Kconfig.erratas
Age
Commit message (
Expand
)
Author
Files
Lines
2022-09-17
riscv: make t-head erratas depend on MMU
Heiko Stuebner
1
-2
/
+2
2022-08-11
riscv: implement Zicbom-based CMO instructions + the t-head variant
Palmer Dabbelt
1
-0
/
+11
2022-08-04
riscv: implement cache-management errata for T-Head SoCs
Heiko Stuebner
1
-0
/
+11
2022-07-01
riscv: Kconfig: Style cleanups
Palmer Dabbelt
1
-1
/
+1
2022-07-01
riscv: Kconfig.erratas: Add comments
Juerg Haefliger
1
-1
/
+1
2022-06-17
riscv: fix dependency for t-head errata
Heiko Stuebner
1
-0
/
+1
2022-05-12
riscv: add memory-type errata for T-Head
Heiko Stuebner
1
-0
/
+21
2022-05-12
riscv: integrate alternatives better into the main architecture
Heiko Stuebner
1
-11
/
+2
2022-03-10
riscv: alternative only works on !XIP_KERNEL
Jisheng Zhang
1
-0
/
+1
2021-05-06
riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y
Vincent Chen
1
-2
/
+2
2021-04-26
riscv: sifive: Apply errata "cip-1200" patch
Vincent Chen
1
-0
/
+11
2021-04-26
riscv: sifive: Apply errata "cip-453" patch
Vincent Chen
1
-0
/
+11
2021-04-26
riscv: sifive: Add SiFive alternative ports
Vincent Chen
1
-0
/
+10
2021-04-26
riscv: Introduce alternative mechanism to apply errata solution
Vincent Chen
1
-0
/
+12