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path: root/arch/arm64/include/asm/tlbflush.h
AgeCommit message (Expand)AuthorFilesLines
2020-08-28arm64: use a common .arch preamble for inline assemblySami Tolvanen1-2/+4
2020-07-15arm64: tlb: Use the TLBI RANGE feature in arm64Zhenyu Ye1-29/+125
2020-07-10arm64: tlb: don't set the ttl value in flush_tlb_page_nosyncZhenyu Ye1-3/+2
2020-07-07arm64: Shift the __tlbi_level() indentation leftCatalin Marinas1-22/+21
2020-07-07arm64: tlb: Set the TTL field in flush_tlb_rangeZhenyu Ye1-6/+8
2020-07-07arm64: Add tlbi_user_level TLB invalidation helperZhenyu Ye1-6/+12
2020-07-07arm64: Add level-hinted TLB invalidation helperMarc Zyngier1-0/+45
2019-08-27arm64: tlb: Ensure we execute an ISB following walk cache invalidationWill Deacon1-0/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2019-06-12arm64: tlbflush: Ensure start/end of address range are aligned to strideWill Deacon1-0/+3
2018-12-26Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-4/+11
2018-11-29arm64: Add workaround for Cortex-A76 erratum 1286807Catalin Marinas1-2/+2
2018-11-27arm64: tlbi: Set MAX_TLBI_OPS to PTRS_PER_PTEWill Deacon1-2/+2
2018-11-26arm64: mm: Don't wait for completion of TLB invalidation when page agingAlex Van Brunt1-2/+9
2018-09-11arm64: tlb: Rewrite stale comment in asm/tlbflush.hWill Deacon1-25/+55
2018-09-11arm64: tlb: Avoid synchronous TLBIs when freeing page tablesWill Deacon1-11/+0
2018-09-11arm64: tlbflush: Allow stride to be specified for __flush_tlb_range()Will Deacon1-6/+9
2018-09-11arm64: tlb: Justify non-leaf invalidation in flush_tlb_range()Will Deacon1-0/+4
2018-09-11arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()Will Deacon1-0/+2
2018-09-11arm64: tlb: Use last-level invalidation in flush_tlb_kernel_range()Will Deacon1-1/+1
2018-07-06arm64: tlbflush: Introduce __flush_tlb_kernel_pgtableChintan Pandya1-0/+7
2018-03-28arm64: tlbflush: avoid writing RES0 bitsPhilip Elcan1-8/+17
2017-12-11arm64: mm: Invalidate both kernel and user ASIDs when performing TLBIWill Deacon1-2/+14
2017-02-01arm64: Work around Falkor erratum 1009Christopher Covington1-3/+15
2016-09-28arm64: tlbflush.h: add __tlbi() macroMark Rutland1-8/+26
2015-10-07arm64: tlb: remove redundant barrier from __flush_tlb_pgtableWill Deacon1-1/+0
2015-10-07arm64: tlbflush: remove redundant ASID casts to (unsigned long)Will Deacon1-5/+4
2015-10-07arm64: flush: use local TLB and I-cache invalidationWill Deacon1-0/+8
2015-07-28arm64: Use last level TLBI for user pte changesCatalin Marinas1-5/+16
2015-07-28arm64: Clean up __flush_tlb(_kernel)_range functionsCatalin Marinas1-26/+21
2015-07-27arm64: move update_mmu_cache() into asm/pgtable.hWill Deacon1-14/+0
2015-06-12arm64: mm: remove reference to tlb.S from comment blockVladimir Murzin1-2/+0
2015-03-14arm64: Invalidate the TLB corresponding to intermediate page table levelsCatalin Marinas1-0/+13
2015-02-26arm64: mm: remove unused functions and variable protoypesYingjoe Chen1-5/+0
2014-07-24arm64: fix soft lockup due to large tlb flush rangeMark Salter1-3/+26
2014-07-24arm64: Fix barriers used for page table modificationsCatalin Marinas1-2/+3
2014-05-09arm64: barriers: make use of barrier options with explicit barriersWill Deacon1-7/+7
2014-05-09arm64: mm: Optimise tlb flush logic where we have >4K granuleSteve Capper1-5/+25
2013-06-14ARM64: mm: THP support.Steve Capper1-0/+2
2012-09-17arm64: TLB maintenance functionalityCatalin Marinas1-0/+122
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