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path: root/arch/arm64/include/asm/sysreg.h
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2022-06-08arm64/sme: Fix tests for 0b1111 value ID registersMark Brown1-2/+2
2022-05-20arm64/sysreg: Generate definitions for FAR_ELxMark Brown1-3/+0
2022-05-20arm64/sysreg: Generate definitions for DACR32_EL2Mark Brown1-1/+0
2022-05-20arm64/sysreg: Generate definitions for CSSELR_EL1Mark Brown1-2/+0
2022-05-20arm64/sysreg: Generate definitions for CPACR_ELxMark Brown1-2/+0
2022-05-20arm64/sysreg: Generate definitions for CONTEXTIDR_ELxMark Brown1-2/+0
2022-05-20arm64/sysreg: Generate definitions for CLIDR_EL1Mark Brown1-1/+0
2022-05-16arm64/sve: Generate ZCR definitionsMark Brown1-7/+0
2022-05-16arm64/sme: Generate defintions for SVCRMark Brown1-4/+0
2022-05-16arm64/sme: Generate SMPRI_EL1 definitionsMark Brown1-3/+0
2022-05-16arm64/sme: Automatically generate SMPRIMAP_EL2 definitionsMark Brown1-1/+0
2022-05-16arm64/sme: Automatically generate SMIDR_EL1 definesMark Brown1-1/+0
2022-05-16arm64/sme: Automatically generate defines for SMCRMark Brown1-10/+0
2022-05-16arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.hMark Brown1-3/+3
2022-05-16arm64/sme: Standardise bitfield names for SVCRMark Brown1-2/+2
2022-05-16arm64/sme: Drop SYS_ from SMIDR_EL1 definesMark Brown1-3/+3
2022-05-16arm64/fp: Rename SVE and SME LEN field name to _WIDTHMark Brown1-2/+2
2022-05-16arm64/fp: Make SVE and SME length register definition match architectureMark Brown1-14/+4
2022-05-16Merge branch 'for-next/sme' into for-next/sysreg-genCatalin Marinas1-0/+67
2022-05-04arm64/sysreg: Generate definitions for SCTLR_EL1Mark Brown1-38/+0
2022-05-04arm64/sysreg: Generate definitions for TTBRn_EL1Mark Brown1-2/+0
2022-05-04arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1Mark Brown1-20/+0
2022-05-04arm64/sysreg: Enable automatic generation of system register definitionsMark Brown1-0/+8
2022-05-04arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro namesMark Brown1-17/+17
2022-05-04arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARMMark Brown1-1/+1
2022-05-04arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1Mark Brown1-21/+32
2022-05-04arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWIMark Brown1-3/+3
2022-05-04arm64/mte: Make TCF field values and naming more standardMark Brown1-7/+7
2022-05-04arm64/mte: Make TCF0 naming and field values more standardMark Brown1-4/+4
2022-05-04arm64/sysreg: Introduce helpers for access to sysreg fieldsMark Brown1-0/+6
2022-04-22arm64/sme: System register and exception syndrome definitionsMark Brown1-0/+67
2022-03-24Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+8
2022-03-14Merge branch 'for-next/spectre-bhb' into for-next/coreWill Deacon1-0/+2
2022-03-14Merge branch 'for-next/fpsimd' into for-next/coreWill Deacon1-1/+3
2022-03-14Merge branch 'for-next/pauth' into for-next/coreWill Deacon1-0/+12
2022-02-25arm64: Always use individual bits in CPACR floating point enablesMark Brown1-2/+0
2022-02-25arm64: Define CPACR_EL1_FPEN similarly to other floating point controlsMark Brown1-0/+4
2022-02-25arm64: Add support of PAuth QARMA3 architected algorithmVladimir Murzin1-0/+12
2022-02-24arm64: Use the clearbhb instruction in mitigationsJames Morse1-0/+1
2022-02-24arm64: Mitigate spectre style branch history side channelsJames Morse1-0/+1
2022-02-15arm64/mm: Consolidate TCR_EL1 fieldsAnshuman Khandual1-4/+0
2022-02-08KVM: arm64: Allow guest to set the OSLK bitOliver Upton1-0/+3
2022-02-08KVM: arm64: Stash OSLSR_EL1 in the cpu contextOliver Upton1-0/+5
2022-01-16Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+1
2021-12-13arm64: add ID_AA64ISAR2_EL1 sys registerJoey Gouly1-0/+15
2021-12-13arm64: cpufeature: add HWCAP for FEAT_AFPJoey Gouly1-0/+1
2021-12-01KVM: arm64: Add minimal handling for the ARMv8.7 PMUMarc Zyngier1-0/+1
2021-11-02Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+3
2021-10-29Merge branch 'for-next/mte' into for-next/coreWill Deacon1-0/+3
2021-10-29Merge branch 'for-next/extable' into for-next/coreWill Deacon1-17/+8
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