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2025-05-13arm64: dts: exynos: gs101: add pmu-intr-gen syscon nodePeter Griffin1-0/+6
Add syscon node for the PMU Interrupt Generation registers. Additionally update the exynos-pmu node to provide a phandle to pmu-intr-gen syscon. These registers are required for CPU hotplug to be functional. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-4-9f64a2657316@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-16arm64: dts: exynos: update all samsung,mode constantsIvaylo Ivanov2-3/+3
Update all samsung,mode property values to account for renaming USI_V2 constants to USI_MODE in the bindings. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250209132043.3906127-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-07arm64: dts: exynos: gs101: Change labels to lower-caseKrzysztof Kozlowski1-11/+11
DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250219085726.70824-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: exynos: gs101: add ACPM protocol nodeTudor Ambarus1-0/+8
Add the ACPM protocol node. ACPM protocol provides interface for all the client drivers making use of the features offered by the Active Power Management (APM) module. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-3-230ba8663a2d@linaro.org [krzysztof: correct alphabetical node placement] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: exynos: gs101: add AP to APM mailbox nodeTudor Ambarus1-0/+9
GS101 has 14 mailbox controllers. Add the AP to APM mailbox node. Mailbox controllers have a shared register that can be used for passing the mailbox messages. The AP to APM mailbox controller is used just as a doorbell mechanism. It raises interrupt to the firmware after the mailbox message has been written to SRAM where the TX/RX rings are defined. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-2-230ba8663a2d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: exynos: gs101: add SRAM nodeTudor Ambarus1-0/+8
SRAM is used by the ACPM protocol to retrieve the ACPM channels information, which includes the TX/RX rings among other channel configuration data. Add the SRAM node. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-1-230ba8663a2d@linaro.org [krzysztof: correct alphabetical node placement] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-15arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)André Draszik1-0/+13
syscon-reboot-mode can be used to indicate the reboot mode for the bootloader. While not sufficient for all boot modes, the boot loader does use SYSIP_DAT0 (PMU + 0x0810) to determine some of the actions it should take. This change helps it deciding what to do in those cases. For complete support, we'll also have to write the boot mode to an NVMEM storage location, but we have no upstream driver for that yet. Nevertheless, this patch is a step towards full support for the boot mode. Note1: Android also uses 'shutdown,thermal' and shutdown,thermal,battery', but that can not be described in DT as ',' is used to denote vendor prefixes. I've left them out from here for that reason. Note2: downstream / bootloader recognizes one more mode: 'dm-verity device corrupted' with value 0x50, but we can not describe that in DT using a property name due to the space, so it's been left out from here as well. This string appears to come from drivers/md/dm-verity-target.c and should probably be changed there in a follow-up patch, so that it can be used in reboot-mode nodes like this one here. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250210-gs101-renppt-dts-v2-3-fb33fda6fc4b@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-15arm64: dts: exynos: gs101: align poweroff writes with downstreamAndré Draszik1-1/+2
For power off, downstream only clears bit 8 and leaves all other bits untouched, whereas this here ends up setting bit 8 and clearing all others, due to how sysconf-poweroff parses the DT. I noticed this discrepancy while debugging some reboot related differences between up- and downstream and it's useful to align the behaviour here. Note: for reboot downstream seems to be incorrectly writing 0x00000002 and not just setting bit 1 (which is the only R/W bit in this register), so we keep that one as-is here. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250210-gs101-renppt-dts-v2-2-fb33fda6fc4b@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-15arm64: dts: exynos: gs101: drop explicit regmap from reboot nodesAndré Draszik1-2/+0
The regmap property for syscon-poweroff and syscon-reboot is unneeded here because the poweroff and reboot nodes are children of syscon already. It also is deprecated. We can just drop it to simplify the DT. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250210-gs101-renppt-dts-v2-1-fb33fda6fc4b@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-04arm64: dts: exynos: gs101-raven: add new board fileAndré Draszik2-0/+30
Raven is Google's code name for Pixel 6 Pro. Similar to Pixel 6 (Oriole), this is also based around its Tensor gs101 SoC. For now, the relevant difference here is the display resolution: 1440 x 3120 instead of 1080 x 2400. Create a new board file to reflect this difference. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-4-a5b90ca2f917@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-04arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsiAndré Draszik2-276/+302
In order to support Pixel 6 (Oriole), Pixel 6 Pro (Raven), Pixel 6a (Bluejay), and all other versions correctly, we have to be able to distinguish them properly as we add support for more features. For example, Raven has a larger display. There are other differences, like battery design capacity, etc. Move all the parts that are common for now into a gs101-pixel-common.dtsi, and just leave the display related things in gs101-oriole.dts. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-3-a5b90ca2f917@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-04arm64: dts: exynos: gs101-oriole: configure simple-framebufferAndré Draszik1-0/+17
The bootloader configures the display hardware for a framebuffer at the given address, let's add a simple-framebuffer node here until we get a proper DRM driver. This has several benefits since it's an OLED display: * energy consumption goes down significantly, as it changes from white (as left by bootloader) to black (linux console), and we generally don't run out of battery anymore when plugged into a USB port * less of a burn-in effect I assume * phone stays cooler due to reduced energy consumption by display Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-2-a5b90ca2f917@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-04arm64: dts: exynos: gs101: disable pinctrl_gsacore nodePeter Griffin1-0/+1
gsacore registers are not accessible from normal world. Disable this node, so that the suspend/resume callbacks in the pinctrl driver don't cause a Serror attempting to access the registers. Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 SoC support") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> To: Rob Herring <robh@kernel.org> To: Krzysztof Kozlowski <krzk+dt@kernel.org> To: Conor Dooley <conor+dt@kernel.org> To: Alim Akhtar <alim.akhtar@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: tudor.ambarus@linaro.org Cc: andre.draszik@linaro.org Cc: kernel-team@android.com Cc: willmcvicker@google.com Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250106-contrib-pg-pinctrl_gsacore_disable-v1-1-d3fc88a48aed@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmodeAndré Draszik1-1/+6
When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCiAndré Draszik1-0/+99
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: gs101: allow stable USB phy Vbus detectionAndré Draszik1-0/+3
For the DWC3 core to reliably detect the connected phy's Vbus state, we need to disable phy suspend. Add snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk to do that. While at it, also add snps,has-lpm-erratum as this is set downstream which implies that the core was configured with LPM Erratum. We should do the same here. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-3-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: gs101: phy region for exynos5-usbdrd is largerAndré Draszik1-1/+1
Turns out there are some additional registers in the phy region, update the DT accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-2-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-29arm64: dts: exynos: gs101: add syscon-poweroff and syscon-reboot nodesPeter Griffin1-0/+15
Reboot of gs101 SoC can be handled by setting the bit(SWRESET_SYSTEM[1]) of SYSTEM_CONFIGURATION register(PMU + 0x3a00). Poweroff of gs101 SoC can be handled by setting bit(DATA[8]) of PAD_CTRL_PWR_HOLD register (PMU + 0x3e9c). Tested using "reboot" and "poweroff -p" commands. Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240628223506.1237523-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-20arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phyAndré Draszik1-0/+7
The USB phy requires various power supplies to work. While we don't have a PMIC driver yet, the supplies should still be added to the DT. Add some placeholders, which will be replaced with the real ones once we implement PMIC. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240618-gs101-usb-regulators-in-dt-v3-1-6a749207052e@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-15arm64: dts: exynos: gs101: reorder properties as per guidelinesAndré Draszik2-12/+12
* 'interrupts' & 'cpus' & 'clocks' are standard/common properties as per the Devicetree Sources (DTS) Coding Style and therefore should be sorted alphabetically within the standard/common section * vendor properties should be last * reg / ranges should be 2nd/3rd (after compatible) * status should be last Do so. Note: I've left the cpus{} node untouched to keep the grouping of relatedd properties. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240611-gs101-dts-cleanup-v1-1-877358cd6536@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrlAndré Draszik1-0/+9
The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add empty clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2André Draszik1-0/+2
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]André Draszik1-0/+4
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) aliveAndré Draszik1-0/+4
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulatorPeter Griffin1-0/+18
Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node. ufs regulator is a stub until full s2mpg11 slave pmic support is added. The gpio defined is for the BOOTLD0 (gs101) signal connected to UFS_EN(s2mpg11) gpio enabled voltage rail for UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodesPeter Griffin1-0/+36
Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: Add the hsi2 sysreg nodePeter Griffin1-0/+6
This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101-oriole: enable USB on this boardAndré Draszik1-0/+24
Pixel 6 (Oriole) has a USB-C connector that can act as host or device. The USB role is detected dynamically using a MAX77759 TCPCI controller, but since there is no driver for the MAX77759, the role is defaulted to peripheral, without any endpoints / ports. This allows Oriole to be configured as a gadget, e.g. using configfs. As PMIC regulators are not implemented yet, we rely on USB LDOs being enabled by the bootloader. A placeholder regulator is used for now. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-2-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: add USB & USB-phy nodesAndré Draszik1-0/+41
Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: enable cmu-hsi2 clock controllerPeter Griffin1-0/+12
Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: enable cmu-hsi0 clock controllerAndré Draszik1-0/+14
Enable the cmu-hsi0 clock controller. It feeds USB. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-2-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: define all PERIC USI nodesTudor Ambarus1-0/+769
Universal Serial Interface (USI) supports three types of serial interface such as UART, SPI and I2C. Each protocol works independently. USI can be configured to work as one of these protocols. Define all the USI nodes from the PERIC blocks (USI0-14), in all their possible configurations. These blocks have the TX/RX FIFO depth of 64 bytes. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: join lines close to 80 charsTudor Ambarus1-8/+4
These lines fit 81 characters, which is pretty close to 80. Join the lines for better readability. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: move pinctrl-* properties after clocksTudor Ambarus1-4/+4
Move the pinctrl-* properties after clocks so that we keep alphabetic order and align with the other similar definitions. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsiTudor Ambarus2-2/+2
The pinctrl nodes are coming from the shared gs101-pinctrl.dtsi, thus the pinctrl-0/names shall stay in dtsi. Move them. Reviewed-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: reorder pinctrl-* propertiesAndré Draszik2-3/+3
The Preferred order for these is pinctrl-0 pinctrl-names. Update the DTSI & DTS accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-29Merge tag 'samsung-dt64-6.9' of ↵Arnd Bergmann3-20/+137
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.9 Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding support for: 1. Multi Core Timer (MCT) clocksource. 2. Several clock controllers (DTS and DT bindings) and use new clocks in several other device nodes. 3. More serial-interface instances: USI8 and USI12 with I2C. Exynos850: 1. SPI and DMA controllers (PL330). * tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add fifosize for UART in Device Tree arm64: dts: exynos: gs101: minor whitespace cleanup arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole arm64: dts: exynos: gs101: define USI12 with I2C configuration arm64: dts: exynos: gs101: enable cmu-peric1 clock controller dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit arm64: dts: exynos: Add SPI nodes for Exynos850 arm64: dts: exynos: Add PDMA node for Exynos850 arm64: dts: exynos: gs101: use correct clocks for usi_uart arm64: dts: exynos: gs101: use correct clocks for usi8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock arm64: dts: exynos: gs101: enable eeprom on gs101-oriole arm64: dts: exynos: gs101: define USI8 with I2C configuration arm64: dts: exynos: gs101: update USI UART to use peric0 clocks arm64: dts: exynos: gs101: enable cmu-peric0 clock controller arm64: dts: exynos: gs101: remove reg-io-width from serial arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node dt-bindings: clock: exynos850: Add PDMA clocks dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-12arm64: dts: exynos: gs101: minor whitespace cleanupKrzysztof Kozlowski2-9/+9
The DTS code coding style expects exactly one space before '{' and around '=' characters. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240208105243.128875-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-orioleAndré Draszik1-0/+10
This bus has three USB-related devices attached to it: 0x25: Maxim 77759 Type-C port controller 0x35: Maxim 20339EWB Surge protection IC 0x36: Maxim 77759 Fuel gauge 0x57: NXP PCA9468 Battery charger 0x66: Maxim 77759 PMIC 0x69: Maxim 77759 Charger where the Maxim 77759 has multiple i2c slave addresses. These don't have (upstream) Linux drivers yet, but nevertheless we can enable the bus so as to allow working on them (and to make i2cdetect / i2cdump / etc. work). Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-8-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: define USI12 with I2C configurationAndré Draszik1-0/+29
On the gs101-oriole board, i2c bus 12 has various USB-related controllers attached to it. Note the selection of the USI protocol is intentionally left for the board dts file. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-7-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: enable cmu-peric1 clock controllerAndré Draszik1-0/+11
Enable the cmu-peric1 clock controller. It feeds additional USI, I3C and PWM interfaces / busses. Note that &sysreg_peric1 needs a clock to be able to access its registers and now that Linux knows about this clock, we need to add it in this commit as well so as to keep &sysreg_peric1 working, so that the clock can be enabled as and when needed. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-6-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01arm64: dts: exynos: gs101: use correct clocks for usi_uartAndré Draszik1-2/+2
Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240130093812.1746512-5-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01arm64: dts: exynos: gs101: use correct clocks for usi8André Draszik1-2/+2
Wrong pclk clocks have been used in this usi8 instance here. For USI and I2C, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI8_USI_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and i2c drivers. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240130093812.1746512-4-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-26arm64: dts: exynos: gs101: sysreg_peric0 needs a clockAndré Draszik1-0/+1
Without the clock running, we can not access its registers, and now that we have it, we should add it here so that it gets enabled as and when needed. Update the DTSI accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240126115517.1751971-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: enable eeprom on gs101-orioleTudor Ambarus1-0/+14
Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-9-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: define USI8 with I2C configurationTudor Ambarus1-0/+29
USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-8-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: update USI UART to use peric0 clocksTudor Ambarus1-10/+4
Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-7-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: enable cmu-peric0 clock controllerTudor Ambarus1-0/+10
Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: remove reg-io-width from serialTudor Ambarus1-1/+0
Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: define Multi Core Timer (MCT) nodePeter Griffin1-0/+20
MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231222165355.1462740-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 11:46:09 +0300