starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333	Thomas Gleixner	1	-13/+1
2017-08-29	ARM: 8690/1: lpae: build TTB control register value from scratch in v7_ttb_setup	Hoeun Ryu	1	-2/+1
2015-06-02	ARM: redo TTBR setup code for LPAE	Russell King	1	-9/+5
2014-09-25	ARM: 8164/1: mm: clear SCTLR.HA instead of setting it for LPAE	Will Deacon	1	-2/+2
2014-09-02	ARM: 8132/1: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET	Konstantin Khlebnikov	1	-1/+0
2014-08-09	ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1	Konstantin Khlebnikov	1	-4/+3
2014-07-24	ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAE	Steven Capper	1	-2/+7
2014-07-18	ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+	Russell King	1	-2/+3
2014-04-25	ARM: 8037/1: mm: support big-endian page tables	Jianguo Wu	1	-5/+13
2013-07-22	ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2	Will Deacon	1	-1/+1
2013-07-15	arm: delete __cpuinit/__CPUINIT usage from all ARM users	Paul Gortmaker	1	-4/+0
2013-05-30	ARM: LPAE: accomodate >32-bit addresses for page table base	Cyril Chemparathy	1	-0/+8
2013-05-30	ARM: LPAE: factor out T1SZ and TTBR1 computations	Cyril Chemparathy	1	-21/+8
2013-05-30	ARM: LPAE: use phys_addr_t in switch_mm()	Cyril Chemparathy	1	-4/+12
2013-04-03	ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead	Will Deacon	1	-1/+2
2013-03-04	ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.id	Ben Dooks	1	-1/+1
2013-02-16	ARM: 7650/1: mm: replace direct access to mm->context.id with new macro	Ben Dooks	1	-1/+1
2012-11-09	ARM: mm: introduce present, faulting entries for PAGE_NONE	Will Deacon	1	-0/+3
2012-11-09	ARM: mm: introduce L_PTE_VALID for page table entries	Will Deacon	1	-1/+1
2011-12-08	ARM: LPAE: MMU setup for the 3-level page table format	Catalin Marinas	1	-0/+150