summaryrefslogtreecommitdiff
path: root/Documentation/arch/riscv
AgeCommit message (Expand)AuthorFilesLines
2024-09-17Merge tag 'docs-6.12' of git://git.lwn.net/linuxLinus Torvalds1-1/+1
2024-09-05Documentation: Fix spelling mistakesAmit Vadhavana1-1/+1
2024-08-29Merge patch series "riscv: mm: Do not restrict mmap address based on hint"Palmer Dabbelt1-16/+0
2024-08-29Revert "RISC-V: mm: Document mmap changes"Charlie Jenkins1-16/+0
2024-08-14RISC-V: hwprobe: Add SCALAR to misaligned perf definesEvan Green1-13/+15
2024-08-14RISC-V: hwprobe: Add MISALIGNED_PERF keyEvan Green1-7/+13
2024-07-26RISC-V: Provide the frequency of time CSR via hwprobePalmer Dabbelt1-0/+2
2024-07-26riscv: Extend sv39 linear mapping max size to 128GStuart Menefy1-5/+6
2024-07-20Merge tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+50
2024-07-12Merge patch series "riscv: Apply Zawrs when available"Palmer Dabbelt1-0/+4
2024-07-12riscv: hwprobe: export Zawrs ISA extensionAndrew Jones1-0/+4
2024-07-11riscv: hwprobe: export highest virtual userspace addressClément Léger1-0/+3
2024-07-01documentation: Fix riscv cmodx exampleCharlie Jenkins1-2/+2
2024-06-26riscv: hwprobe: export Zcmop ISA extensionClément Léger1-0/+4
2024-06-26riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensionsClément Léger1-0/+20
2024-06-26riscv: hwprobe: export Zimop ISA extensionClément Léger1-0/+4
2024-05-31riscv: hwprobe: add zve Vector subextensions into hwprobe interfaceAndy Chiu1-0/+15
2024-05-30Documentation: RISC-V: uabi: Only scalar misaligned loads are supportedPalmer Dabbelt1-1/+3
2024-04-30Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ...Palmer Dabbelt2-0/+99
2024-04-29riscv: hwprobe: export Zihintpause ISA extensionClément Léger1-0/+4
2024-04-18documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctlCharlie Jenkins2-0/+99
2024-03-14docs: riscv: Define behavior of mmapCharlie Jenkins1-11/+5
2024-01-17Merge tag 'docs-6.8-2' of git://git.lwn.net/linuxLinus Torvalds1-1/+1
2024-01-11docs: kernel_feat.py: fix potential command injectionVegard Nossum1-1/+1
2024-01-10Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt1-0/+13
2024-01-10riscv: hwprobe: export Zicond extensionClément Léger1-0/+5
2024-01-10riscv: hwprobe: export Zacas ISA extensionClément Léger1-0/+4
2024-01-10riscv: hwprobe: export Ztso ISA extensionClément Léger1-0/+4
2024-01-10Merge patch series "RISC-V: hwprobe: Introduce which-cpus"Palmer Dabbelt1-7/+21
2024-01-03RISC-V: hwprobe: Introduce which-cpus flagAndrew Jones1-2/+15
2024-01-03RISC-V: hwprobe: Clarify cpus size parameterAndrew Jones1-7/+8
2023-12-13riscv: hwprobe: export Zfa ISA extensionClément Léger1-0/+4
2023-12-13riscv: hwprobe: export Zvfh[min] ISA extensionsClément Léger1-0/+8
2023-12-13riscv: hwprobe: export Zhintntl ISA extensionClément Léger1-0/+3
2023-12-13riscv: hwprobe: export Zfh[min] ISA extensionsClément Léger1-0/+6
2023-12-13riscv: hwprobe: export vector crypto ISA extensionsClément Léger1-0/+30
2023-12-13riscv: hwprobe: add support for scalar crypto ISA extensionsClément Léger1-0/+27
2023-12-13riscv: hwprobe: export missing Zbc ISA extensionClément Léger1-0/+3
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-0/+20
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-0/+6
2023-10-10docs: move riscv under archCosta Shulyupin10-0/+767