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The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.
The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add the bdisp (2D blitter for STMicroelectronics SoC) dt nodes for the
first of the two bdisp devices, defining register address, interrupt and
clock.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This also incorporates the STiH410.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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To enable SMP when booting via u-boot we need to specify the
newly implemented cpu-release-addr DT property for cores 2 & 3.
Cores 0 & 1 are inherited from stih407-family.dtsi.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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To enable SMP when booting via u-boot we need to specify the
newly implemented cpu-release-addr DT property.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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mtsin0 channel can only be configured for parallel data transfer.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsout1 channel can only be configured for serial data tranfer.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsout0 channel can be configured for either serial or parallel
data transfer. Both pin configurations are provided.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin5 can only be configured for serial data transfer. However
depending on board design, two alternate tsin5 pin configurations
are available, both in pin-controller-front0.
pinctrl_tsin5_serial_alt1 is brought out on B2120 reference
design as TSD on NIMB slot of the B2004A daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin4 can only be configured for serial data transfer. However
depending on board design, two alternate pin configurations
are available. One in pin-controller-front0 and the other in
pin-controller-front1.
pinctrl_tsin4_serial_alt3 is brought out on B2120 reference
design as TSC on NIMA slot of the B2004A daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin3 channel can only be configured for serial data transfer.
On B2120 reference design tsin3 is brought out as TSB on the NIMB
slot of the B2004A daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin2 channel can be configured for either serial or parallel data
transfer. This patch adds the pinctrl config for both possibilities.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin1 channel can be configured for either serial or parallel data
transfer. This patch adds the pinctrl config for both possibilities.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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tsin0 and be configured as either serial or parallel. This patch
adds the pinctrl config for both possiblities. On B2120 reference
design tsin0 is brought out as TSA on the NIMA slot of the B2004A
daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The adv7511 IRQ is low level triggered, not falling edge triggered. The
wrong sense configuration results in no interrupt being triggered at
all, breaking hotplug detection. Fix it.
Reported-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Merge "pxa-dt for v4.3" from Robert Jarzmik:
This device-tree pxa update brings :
- dma nodes after dmaengine pxa_dma driver merge
- camera driver
- usb host controller
* tag 'tags/pxa-dt-4.3' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: fix power i2c definition
ARM: dts: pxa: add the usb host controller
ARM: dts: pxa: add embedded pxa camera capture interface
ARM: dts: pxa: add dma pxamci nodes to pxa3xx
ARM: dts: pxa: add dma engine node to pxa3xx-nand
ARM: dts: pxa: add dma controller
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Terasic DE0 Atlas board is also known as the DE0-Nano board.
This patch adds the DTS board file for the DE0-Nano Sockit board, and not
the DE0 Nano "Development Board".
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: Updated skew settings for the gmac1 node as this board is using the
KSZ9031 PHY instead of the 9021 PHY.
v2: use stdpath-out for console and remove comment regarding u-boot ethaddr
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Add wl1251 support via pdata-quirks as it's driver lacks DT
support. MMC3 is marked disabled in DT so that MMC3 instance of
hsmmc driver is probed using platform data with special card init
callback.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add backlight support via pdata-quirks as it's driver lacks DT support.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This adds missing bits for EHCI HS USB host support and 32k clock
buffer control for the wg7210 bt+wifi module.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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- add pandora specific compatible name
- fix mmc2 card detect polarity
- fix mmc1 and mmc2 write protect polarity
- disable write protect pins because of production issue and add an
explanation why they are disabled
- fix NAND partition name to reflect the correct address
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Palmas on OMAP5uevm has support for power button, so enable it.
Signed-off-by: Aparna Balasubramanian <aparnab@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add serialN aliases for all 6 UART instances on
the AM437x SoC so each board's .dts file does not
have to define its own aliases.
Remove the alias added for am437x-gp-evm.dts now
that we have the aliases defined in am4372.dtsi
file.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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phyBOARD-WEGA-AM335x represents a direct soldered
combination of a phyCORE-AM335x SoM and carrier board.
Different kind of SoM options can be connected to
the wega carrier board. So we created a separate
wega dtsi file. The final dts contains the actual
SoM on the carrier board.
WEGA carrier board features:
* ETH phy on carrier board: 1x MII
* 1x CAN
* 2x UART
* USB0 (device)
* USB1 (host)
* mSD slot
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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phyCORE-AM335x is a SoM (System on Module) containing
a AM335x SOC. The module can be connected to different
carrier boards.
Some hardware parts are configurable on the phyCORE-AM335x.
So they are disabled on default in this som dtsi file.
They will be enabled in the board dts files, when populated.
* RAM up to 1GiB
* PMIC
* NAND flash up to 1GiB
* Eth PHY on SOM: 1x RMII
* SPI NOR flash 8MiB (optional)
* i2c RTC (optional)
* i2c EEPROM 4kiB (optional)
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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In tsc2046 touch driver, the values such as ti,x-min is defined as a u16
value. the driver use API of_property_read_u16() read the value. For these
u16 value, the dts entry should be like:
property = /bits/ 16 <0x5000>;
This describes the property as a u16 value.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Use stdout-path dts property for kernel console.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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This adds basic chip support for Mediatek 6580.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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This adds a DT binding documentation for the MT6580 SoC from Mediatek.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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We used to provide dummy clocks for the UART. Now that we have
common clock support we can provide the real clocks to the UART.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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The MT8135 eval board contains a MT6397 PMIC. This adds the
corresponding device node to the dts file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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This adds the pmic wrapper node to the MediaTek MT8135 dtsi file.
This unit is used to access the PMIC on MediaTek boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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This patch adds MT8135 clock controllers into device tree.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "Rockchip dts changes for 4.3, part1" from Heiko Stuebner:
This adds the board for the Netxeon R89 used in different TV-boxes and
the initial support for two Chromebooks from the veyron family.
Additionally a non-critical fix for the watchdog irq on rk3288, addition
of the gmac reset line, a ramp delay for the cpu regulator on the firefly
board and cpu affinity for the arm-pmu spi irqs.
* tag 'v4.3-rockchip32-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add rk3288 arm-pmu irq affinity
dt-bindings: document rk3368 R88 board from Rockchip
ARM: dts: rockchip: add missing device_type = "memory" to boards
ARM: dts: rockchip: add veyron-pinky board
ARM: dts: rockchip: add veyron-jerry board
ARM: dts: rockchip: add shared rk3288-veyron files
ARM: dts: Add sbs-battery dts fragment used by chromebooks
ARM: dts: rockchip: add Netxeon R89 board
dt-bindings: add vendor prefix for Netxeon Technology
ARM: dts: rockchip: fix rk3288 watchdog irq
ARM: dts: rockchip: Add ramp delay for vdd_cpu in firefly board dts
ARM: dts: rockchip: Add STMMAC reset signal in GMAC interface for rk3288
Signed-off-by: Olof Johansson <olof@lixom.net>
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next/dt
Merge "Broadcom Device Tree changes for 4.3 (part 1)" from Florian Fainelli:
This pull request contains two changes:
- Ray adds the relevant clocks device tree nodes for Cygnus SoCs
- Rafal enables UART0 on BCM5301X routers where it has been verified to work
correctly
* tag 'arm-soc/for-4.3/dts' of http://github.com/broadcom/stblinux:
ARM: BCM5301X: Enable UART0 on tested devices
ARM: dts: enable clock support for Broadcom Cygnus
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "ARM: mvebu: dt changes for v4.3" from Gregory Clement:
mvebu dt changes for v4.3 (part #1)
- Update Armada 388 GP description
- Add Buffalo Linkstation LS-WXL and LS-WSXL
- Fine-tune the L2 configuration for cortex A9 based SoC
- Update XOR definition for Armada 38x and 39x SoC
* tag 'mvebu-dt-4.3-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: update EEPROM description of Armada 388 GP
ARM: mvebu: fix description of pwr-sata0 regulator on Armada 388 GP
ARM: dts: add buffalo linkstation ls-wvl/vl
ARM: dts: add buffalo linkstation ls-wxl/wsxl
ARM: mvebu: use DT properties to fine-tune the L2 configuration
ARM: mvebu: use armada-380-xor on Armada 38x and 39x
Signed-off-by: Olof Johansson <olof@lixom.net>
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into next/dt
Merge "LPC18xx DTS changes for 4.3" from Joachim Eastwood:
This patch set adds DT nodes for all the drivers that went upstream in
4.2 and should represent the bulk of DTS changes for 4.3. All nodes
added are documented and some of patches carries a ack from subsystem
maintainer. It also features updates to the EA4357 dev- kit and a new
board from Ezequiel Garcia.
Note that there might be one more batch of DTS changes for 4.3 if any
new drivers goes upstream and also some changes for the Hitex eval board
might come.
* 'lpc18xx_43xx_dts_4.3' of https://github.com/manabian/linux-lpc:
ARM: dts: add DT for CIAA LPC4337 industrial computer
of: add vendor prefix for CIAA project
ARM: dts: lpc4357-ea4357: add uart3
ARM: dts: lpc4357-ea4357: add ethernet
ARM: dts: lpc4357-ea4357: add gpio joystick
ARM: dts: lpc4357-ea4357: add mmcsd
ARM: dts: lpc4357-ea4357: add pinctrl and uart0 muxing
ARM: dts: lpc18xx: add usb nodes
ARM: dts: lpc18xx: add ethernet node
ARM: dts: lpc18xx: add creg (syscon) node
ARM: dts: lpc18xx: add mmcsd node
ARM: dts: lpc18xx: add can nodes
ARM: dts: lpc18xx: add ssp nodes
ARM: dts: lpc18xx: add gpio node
ARM: dts: lpc18xx: add pinctrl node
ARM: dts: lpc18xx: add uart new compat string and clk names
ARM: dts: lpc18xx: add cgu and ccu clock-controller nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
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The rk3288 uses spi irqs for the arm-pmu on individual cpu cores, so needs
the affinity to them defined.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
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The initial board containing the rk3368 ARM64 soc.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The memory node is supposed to contain a device_type property marking
it as memory. The currently included boards miss this property.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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While pinky was one of the earlier development models, is on the list
of endangered species today and nearly extinct, I want to keep mine
around for the foreseeable future after spending all the time making a
nice hole into the base below the dut-connector.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The Hisense Chromebook C11, also named jerry.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
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This adds the shared devicetree files for the Veyron device family.
They are split, as not all veyron devices are chromebooks and
not all contain a sd-card slot.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
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