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| author | Peter Griffin <peter.griffin@linaro.org> | 2015-06-10 17:04:00 +0300 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 12:03:09 +0300 |
| commit | 855617d6aa3460a75a8c773a883a573fa90a54a8 (patch) | |
| tree | 03d2953b31d5feb8185184facb994e82764cb03c | |
| parent | 71cae849b974e899bab0ac348026cdde10fdf61e (diff) | |
| download | linux-855617d6aa3460a75a8c773a883a573fa90a54a8.tar.xz | |
ARM: STi: DT: Add STiH407 family tsin2 pinctrl configuration
tsin2 channel can be configured for either serial or parallel data
transfer. This patch adds the pinctrl config for both possibilities.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stih407-pinctrl.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index aaf370fffcd3..fc6097ca5b15 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -495,6 +495,34 @@ }; }; }; + + tsin2 { + pinctrl_tsin2_parallel: tsin2_parallel { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin2_serial: tsin2_serial { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 { |