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2020-11-26ARM: dts: stm32: enable HASH by default on stm32mp15Lionel Debieve2-0/+8
Enable HASH1 device for HASH accelerated support on stm32mp15 STMicroelectronics platforms. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26ARM: dts: stm32: Add LP timer wakeup-source on stm32mp151Fabrice Gasnier1-0/+5
LP timer can be used to wakeup from stop mode on stm32mp151. Add wakeup-source properties to all LP timer instances. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26ARM: dts: stm32: Add LP timer irqs on stm32mp151Fabrice Gasnier1-0/+5
Add all LP timer irqs on stm32mp151. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26ARM: dts: stm32: update sdmmc IP version for STM32MP15Yann Gautier1-3/+3
Update the IP version to v2.0, which supports linked lists in internal DMA, and is present in STM32MP1 SoCs. The mmci driver supports the v2.0 periph id since 7a2a98be672b ("mmc: mmci: Add support for sdmmc variant revision 2.0"), so it's now Ok to add it into the SoC device tree to benefit from the improved DMA support. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26ARM: dts: stm32: Harmonize EHCI/OHCI DT nodes name on stm32mp15Serge Semin1-2/+2
In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Amelie Delaunay <amelie.delaunay@st.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for ↵Matthias Kaehlcke4-3/+64
pp3300_hub The trogdor design has two options for supplying the 'pp3300_hub' power rail, it can be supplied by 'pp3300_l7c' or 'pp3300_a'. The 'pp3300_a' path includes a load switch that can be controlled through GPIO84. Initially trogdor boards used 'pp3300_l7c' to power the USB hub, newer revisions (will) use 'pp3300_a' as supply for 'pp3300_hub'. Add a DT node for the 'pp3300_a' path and a pinctrl entry for the GPIO. Make this path the default and keep trogdor rev1, lazor rev0 and rev1 on 'pp3300_l7c'. These earlier revisions also allocated the GPIO to the purpose of controlling the power switch, so there is no need to limit the pinctrl config to newer revisions. Remove the platform-wide 'always/boot-on' properties from 'pp3300_l7c' and add them to the boards that use this supply. Also delete the 'always/boot-on' properties of 'pp3300_hub' for these boards. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201124164714.v4.1.I0ed4abdd2b2916fbedf76be254bc3457fb8b9655@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: add config for Broadcom BCM4908 SoCsRafał Miłecki2-0/+9
Add ARCH_BCM4908 config that can be used for compiling DTS files. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS filesRafał Miłecki4-0/+256
They don't descibe hardware fully yet but it's enough to boot a system. Some missing blocks: 1. PMC (Power Management Controller?) 2. Ethernet 3. Crypto 4. Thermal Asus DTS is missing defining full NAND partitions layout and buttons. Further changes will fill those gaps as soon as required bindings will be found / tested / added. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25dt-bindings: arm: bcm: document BCM4908 bindingsRafał Miłecki1-0/+38
BCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408. It's mostly used in home routers and often replaces Northstar in vendors portfolio. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25arm64: tegra: Rename ADMA device nodes for Tegra210Sameer Pujar4-4/+4
DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$". This is a preparatory patch to use YAML doc format for ADMA. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERMThierry Reding1-1/+3
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet <kwizart@gmail.com> Suggested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zonesNicolas Chauvet1-0/+12
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing gpu-throt-level to Tegra210 socthermNicolas Chauvet1-0/+1
On Jetson TX1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zonesNicolas Chauvet1-0/+10
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix DT binding for IO High Voltage entryVidya Sagar1-2/+2
Fix the device-tree entry that represents I/O High Voltage property by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former entry is deprecated. Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix GIC400 missing GICH/GICV register regionsMarc Zyngier1-1/+3
GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing CPU PMUs on Tegra186Marc Zyngier1-6/+22
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix Tegra234 VDK node namesJon Hunter1-3/+3
When the device-tree board file was added for the Tegra234 VDK simulator it incorrectly used the names 'cbb' and 'sdhci' instead of 'bus' and 'mmc', respectively. The names 'bus' and 'mmc' are required by the device-tree json-schema validation tools. Therefore, fix this by renaming these nodes accordingly. Fixes: 639448912ba1 ("arm64: tegra: Initial Tegra234 VDK support") Reported-by: Ashish Singhal <ashishsingha@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Wrong AON HSP reg property sizeDipen Patel1-1/+1
The AON HSP node's "reg" property size 0xa0000 will overlap with other resources. This patch fixes that wrong value with correct size 0x90000. Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Dipen Patel <dipenp@nvidia.com> Fixes: a38570c22e9d ("arm64: tegra: Add nodes for TCU on Tegra194") Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1JC Kuo1-10/+10
USB host mode is broken on the OTG port of Jetson TX1 platform because the USB_VBUS_EN0 regulator (regulator@11) is being overwritten by the vdd-cam-1v2 regulator. This commit rearranges USB_VBUS_EN0 to be regulator@14. Fixes: 257c8047be44 ("arm64: tegra: jetson-tx1: Add camera supplies") Cc: stable@vger.kernel.org Signed-off-by: JC Kuo <jckuo@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Correct the UART for Jetson Xavier NXJon Hunter1-1/+1
The Jetson Xavier NX board routes UARTA to the 40-pin header and UARTC to a 12-pin debug header. The UARTs can be used by either the Tegra Combined UART (TCU) driver or the Tegra 8250 driver. By default, the TCU will use UARTC on Jetson Xavier NX. Currently, device-tree for Xavier NX enables the TCU and the Tegra 8250 node for UARTC. Fix this by disabling the Tegra 8250 node for UARTC and enabling the Tegra 8250 node for UARTA. Fixes: 3f9efbbe57bc ("arm64: tegra: Add support for Jetson Xavier NX") Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Disable the ACONNECT for Jetson TX2Jon Hunter1-12/+0
Commit ff4c371d2bc0 ("arm64: defconfig: Build ADMA and ACONNECT driver") enable the Tegra ADMA and ACONNECT drivers and this is causing resume from system suspend to fail on Jetson TX2. Resume is failing because the ACONNECT driver is being resumed before the BPMP driver, and the ACONNECT driver is attempting to power on a power-domain that is provided by the BPMP. While a proper fix for the resume sequencing problem is identified, disable the ACONNECT for Jetson TX2 temporarily to avoid breaking system suspend. Please note that ACONNECT driver is used by the Audio Processing Engine (APE) on Tegra, but because there is no mainline support for APE on Jetson TX2 currently, disabling the ACONNECT does not disable any useful feature at the moment. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variantSibi Sankar1-0/+5
Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support frequencies upto 2.5 GHz. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1606198876-3515-2-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-liteSibi Sankar1-0/+18
Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC since the gold cores only support frequencies upto 2.1 GHz. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1606198876-3515-1-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: dts: qcom: sc7180-trogdor: add "pen-insert" label for trogdorTerry Hsiao1-1/+1
Add a label to the "pen-insert" node in sc7180-trogdor.dtsi Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Terry Hsiao <terry_hsiao@compal.corp-partner.google.com> Link: https://lore.kernel.org/r/20201116083014.547-1-terry_hsiao@compal.corp-partner.google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: qcom: sc7180: trogdor: Add ADC nodes and thermal zone for charger ↵Antony Wang1-0/+36
thermistor Trogdor has a thermistor to monitor the temperature of the charger IC. Add the ADC (monitor) nodes and a thermal zone for this thermistor. Signed-off-by: Antony Wang <antony_wang@compal.corp-partner.google.com> [mka: tweaked commit message] Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20201030084840.1.If389f211a8532b83095ff8c66ec181424440f8d6@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: dts: qcom: pm6150x: add ADC_TM definitionsJishnu Prakash2-0/+34
Add ADC_TM peripheral definitions for PM6150 and PM6150L. Add ADC peripheral definition for PM6150l, which is needed for ADC_TM. Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> Link: https://lore.kernel.org/r/1602160825-10414-2-git-send-email-jprakash@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: sdm845: Limit ipa iommu streamsBjorn Andersson1-1/+2
The Android and Windows firmware does not accept the use of 3 as a mask to cover the IPA streams. But with 0x721 being related to WiFi and 0x723 being unsed the mapping can be reduced to just cover 0x720 and 0x722, which is accepted. Acked-by: Alex Elder <elder@linaro.org> Tested-by: Alex Elder <elder@linaro.org> Fixes: e9e89c45bfeb ("arm64: dts: sdm845: add IPA iommus property") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201123052305.157686-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: fix indentation error in sm8250 cpu nodesJonathan Marek1-17/+17
Use tabs instead of 6 spaces. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20201123144016.19596-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: sm8150-mtp: Enable WiFi nodeJonathan Marek1-0/+9
Enable the WiFi node and specify its supply regulators. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> [bjorn: Extracted patch from larger HDK patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201121055808.582401-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: sm8150: Add wifi nodeJonathan Marek1-0/+23
Add a node for the WCN3990 WiFi module. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> [bjorn: Extracted patch from larger "misc" patch, added qdss clock] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201121055808.582401-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: sm8150-mtp: Specify remoteproc firmwareBjorn Andersson1-0/+8
Point the various remoteprocs of SM8150 MTP to a place with the platform specific firmware. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201121055603.582281-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add gpio-line-namesMichael Klein1-0/+64
Add gpio-line-names as documented in the Banana Pi wiki [1] and in the schematics [2]. [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define [2]: https://drive.google.com/file/d/0B4PAo2nW2KfnMW5sVkxWSW9qa28/view Signed-off-by: Michael Klein <michael@fossekall.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201123114535.1605939-1-michael@fossekall.de
2020-11-24arm64: dts: sdm845: Add iommus property to qupStephen Boyd2-0/+4
The SMMU that sits in front of the QUP needs to be programmed properly so that the i2c geni driver can allocate DMA descriptors. Failure to do this leads to faults when using devices such as an i2c touchscreen where the transaction is larger than 32 bytes and we use a DMA buffer. arm-smmu 15000000.iommu: Unexpected global fault, this could be serious arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 Add the right SID and mask so this works. Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Caleb Connolly <caleb@connolly.tech> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> [bjorn: Define for second QUP as well, be more specific in sdm845.dtsi] Link: https://lore.kernel.org/r/20201122034149.626045-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: qcom: sort sm8150 usb_2 nodeJonathan Marek1-7/+7
Fix an error introduced resolving conflicts with camnoc_virt node. Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20201124041003.3600-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"Jisheng Zhang1-2/+2
This is to remove similar errors as below: OF: /.../gpio-port@0: could not find phandle Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support") explained the reason of above errors well and added the generic "ngpios" property, let's use it. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hi3660: Harmonize DWC USB3 DT nodes nameSerge Semin1-1/+1
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yamlZhen Lei1-4/+4
The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by pl011.yamlZhen Lei1-4/+4
The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by spi-pl022.yamlZhen Lei3-8/+8
The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the UART devicesZhen Lei2-3/+3
Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the usb devicesZhen Lei3-6/+6
Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the SMMU devicesZhen Lei2-6/+6
Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: place clock-names "biu" before "ciu"Zhen Lei1-1/+1
Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: remove unused property pinctrl-namesZhen Lei1-2/+0
uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names" can be deleted. In fact, the property "pinctrl-names" depends on the property "pinctrl-0". So the errors similar to the following will be reported by pinctrl-consumer.yaml. serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: write the values of property-units into a uint32 arrayZhen Lei3-7/+8
Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml. ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: separate each group of data in the property "reg"Zhen Lei2-76/+76
Do not write the "reg" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \ 6291456] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the ITS devicesZhen Lei3-13/+13
Change the node name of the ITS devices to match "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although "interrupt-controller" is allowed, but "msi-controller" is preferred. Otherwise, "interrupt-controller@b7000000: False schema does not allow" will be reported by arm,gic-v3.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24ARM: dts: hisilicon: fix errors detected by syscon.yamlZhen Lei1-1/+1
The DT binding for system controller is not allowed to contain only the compatible string "syscon", the Hisilicon peripheral subsystem controller should add compatible string "hisilicon,peri-subctrl". Otherwise, the error "compatible: ['syscon'] is too short" will be reported. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24ARM: dts: hisilicon: fix errors detected by spi-pl022.yamlZhen Lei1-6/+6
1. Change clock-names to "sspclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 17:32:14 +0300