diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/skylake/floating-point.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/skylake/floating-point.json | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json index eb83fa537e7d..4d494a5cabbf 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -32,6 +32,14 @@ "UMask": "0x20" }, { + "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", @@ -48,6 +56,13 @@ "UMask": "0x2" }, { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "2000003", + "UMask": "0xfc" + }, + { "BriefDescription": "Cycles with any input/output SSE or FP assist", "CounterMask": "1", "EventCode": "0xCA", |