diff options
Diffstat (limited to 'drivers/soc')
71 files changed, 3245 insertions, 1108 deletions
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 6a8daeb8c4b9..a2d65adffb80 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -23,11 +23,13 @@ source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" +source "drivers/soc/sophgo/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" +source "drivers/soc/vt8500/Kconfig" source "drivers/soc/xilinx/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 2037a8695cb2..c9e689080ceb 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -29,9 +29,11 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ +obj-y += sophgo/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-y += versatile/ +obj-y += vt8500/ obj-y += xilinx/ diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index a6453ffeb753..d862e30a244e 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -14,11 +14,6 @@ static DEFINE_MUTEX(measure_lock); -#define MSR_CLK_DUTY 0x0 -#define MSR_CLK_REG0 0x4 -#define MSR_CLK_REG1 0x8 -#define MSR_CLK_REG2 0xc - #define MSR_DURATION GENMASK(15, 0) #define MSR_ENABLE BIT(16) #define MSR_CONT BIT(17) /* continuous measurement */ @@ -33,23 +28,34 @@ static DEFINE_MUTEX(measure_lock); #define DIV_STEP 32 #define DIV_MAX 640 -#define CLK_MSR_MAX 128 - struct meson_msr_id { struct meson_msr *priv; unsigned int id; const char *name; }; +struct msr_reg_offset { + unsigned int duty_val; + unsigned int freq_ctrl; + unsigned int duty_ctrl; + unsigned int freq_val; +}; + +struct meson_msr_data { + struct meson_msr_id *msr_table; + unsigned int msr_count; + const struct msr_reg_offset *reg; +}; + struct meson_msr { struct regmap *regmap; - struct meson_msr_id msr_table[CLK_MSR_MAX]; + struct meson_msr_data data; }; #define CLK_MSR_ID(__id, __name) \ [__id] = {.id = __id, .name = __name,} -static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { +static const struct meson_msr_id clk_msr_m8[] = { CLK_MSR_ID(0, "ring_osc_out_ee0"), CLK_MSR_ID(1, "ring_osc_out_ee1"), CLK_MSR_ID(2, "ring_osc_out_ee2"), @@ -98,7 +104,7 @@ static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { CLK_MSR_ID(63, "mipi_csi_cfg"), }; -static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { +static const struct meson_msr_id clk_msr_gx[] = { CLK_MSR_ID(0, "ring_osc_out_ee_0"), CLK_MSR_ID(1, "ring_osc_out_ee_1"), CLK_MSR_ID(2, "ring_osc_out_ee_2"), @@ -168,7 +174,7 @@ static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { CLK_MSR_ID(82, "ge2d"), }; -static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { +static const struct meson_msr_id clk_msr_axg[] = { CLK_MSR_ID(0, "ring_osc_out_ee_0"), CLK_MSR_ID(1, "ring_osc_out_ee_1"), CLK_MSR_ID(2, "ring_osc_out_ee_2"), @@ -242,7 +248,7 @@ static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { CLK_MSR_ID(109, "audio_locker_in"), }; -static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { +static const struct meson_msr_id clk_msr_g12a[] = { CLK_MSR_ID(0, "ring_osc_out_ee_0"), CLK_MSR_ID(1, "ring_osc_out_ee_1"), CLK_MSR_ID(2, "ring_osc_out_ee_2"), @@ -358,7 +364,7 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { CLK_MSR_ID(122, "audio_pdm_dclk"), }; -static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { +static const struct meson_msr_id clk_msr_sm1[] = { CLK_MSR_ID(0, "ring_osc_out_ee_0"), CLK_MSR_ID(1, "ring_osc_out_ee_1"), CLK_MSR_ID(2, "ring_osc_out_ee_2"), @@ -488,10 +494,304 @@ static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { CLK_MSR_ID(127, "csi2_data"), }; +static const struct meson_msr_id clk_msr_c3[] = { + CLK_MSR_ID(0, "sys_clk"), + CLK_MSR_ID(1, "axi_clk"), + CLK_MSR_ID(2, "rtc_clk"), + CLK_MSR_ID(3, "p20_usb2_ckout"), + CLK_MSR_ID(4, "eth_mpll_test"), + CLK_MSR_ID(5, "sys_pll"), + CLK_MSR_ID(6, "cpu_clk_div16"), + CLK_MSR_ID(7, "ts_pll"), + CLK_MSR_ID(8, "fclk_div2"), + CLK_MSR_ID(9, "fclk_div2p5"), + CLK_MSR_ID(10, "fclk_div3"), + CLK_MSR_ID(11, "fclk_div4"), + CLK_MSR_ID(12, "fclk_div5"), + CLK_MSR_ID(13, "fclk_div7"), + CLK_MSR_ID(15, "fclk_50m"), + CLK_MSR_ID(16, "sys_oscin32k_i"), + CLK_MSR_ID(17, "mclk_pll"), + CLK_MSR_ID(19, "hifi_pll"), + CLK_MSR_ID(20, "gp0_pll"), + CLK_MSR_ID(21, "gp1_pll"), + CLK_MSR_ID(22, "eth_mppll_50m_ckout"), + CLK_MSR_ID(23, "sys_pll_div16"), + CLK_MSR_ID(24, "ddr_dpll_pt_clk"), + CLK_MSR_ID(26, "nna_core"), + CLK_MSR_ID(27, "rtc_sec_pulse_out"), + CLK_MSR_ID(28, "rtc_osc_clk_out"), + CLK_MSR_ID(29, "debug_in_clk"), + CLK_MSR_ID(30, "mod_eth_phy_ref_clk"), + CLK_MSR_ID(31, "mod_eth_tx_clk"), + CLK_MSR_ID(32, "eth_125m"), + CLK_MSR_ID(33, "eth_rmii"), + CLK_MSR_ID(34, "co_clkin_to_mac"), + CLK_MSR_ID(36, "co_rx_clk"), + CLK_MSR_ID(37, "co_tx_clk"), + CLK_MSR_ID(38, "eth_phy_rxclk"), + CLK_MSR_ID(39, "eth_phy_plltxclk"), + CLK_MSR_ID(40, "ephy_test_clk"), + CLK_MSR_ID(66, "vapb"), + CLK_MSR_ID(67, "ge2d"), + CLK_MSR_ID(68, "dewarpa"), + CLK_MSR_ID(70, "mipi_dsi_meas"), + CLK_MSR_ID(71, "dsi_phy"), + CLK_MSR_ID(79, "rama"), + CLK_MSR_ID(94, "vc9000e_core"), + CLK_MSR_ID(95, "vc9000e_sys"), + CLK_MSR_ID(96, "vc9000e_aclk"), + CLK_MSR_ID(97, "hcodec"), + CLK_MSR_ID(106, "deskew_pll_clk_div32_out"), + CLK_MSR_ID(107, "mipi_csi_phy_clk_out[0]"), + CLK_MSR_ID(108, "mipi_csi_phy_clk_out[1]"), + CLK_MSR_ID(110, "spifc"), + CLK_MSR_ID(111, "saradc"), + CLK_MSR_ID(112, "ts"), + CLK_MSR_ID(113, "sd_emmc_c"), + CLK_MSR_ID(114, "sd_emmc_b"), + CLK_MSR_ID(115, "sd_emmc_a"), + CLK_MSR_ID(116, "gpio_msr_clk"), + CLK_MSR_ID(117, "spicc_b"), + CLK_MSR_ID(118, "spicc_a"), + CLK_MSR_ID(122, "mod_audio_pdm_dclk_o"), + CLK_MSR_ID(124, "o_earcrx_dmac_clk"), + CLK_MSR_ID(125, "o_earcrx_cmdc_clk"), + CLK_MSR_ID(126, "o_earctx_dmac_clk"), + CLK_MSR_ID(127, "o_earctx_cmdc_clk"), + CLK_MSR_ID(128, "o_tohdmitx_bclk"), + CLK_MSR_ID(129, "o_tohdmitx_mclk"), + CLK_MSR_ID(130, "o_tohdmitx_spdif_clk"), + CLK_MSR_ID(131, "o_toacodec_bclk"), + CLK_MSR_ID(132, "o_toacodec_mclk"), + CLK_MSR_ID(133, "o_spdifout_b_mst_clk"), + CLK_MSR_ID(134, "o_spdifout_mst_clk"), + CLK_MSR_ID(135, "o_spdifin_mst_clk"), + CLK_MSR_ID(136, "o_audio_mclk"), + CLK_MSR_ID(137, "o_vad_clk"), + CLK_MSR_ID(138, "o_tdmout_d_sclk"), + CLK_MSR_ID(139, "o_tdmout_c_sclk"), + CLK_MSR_ID(140, "o_tdmout_b_sclk"), + CLK_MSR_ID(141, "o_tdmout_a_sclk"), + CLK_MSR_ID(142, "o_tdminb_1b_sclk"), + CLK_MSR_ID(143, "o_tdmin_1b_sclk"), + CLK_MSR_ID(144, "o_tdmin_d_sclk"), + CLK_MSR_ID(145, "o_tdmin_c_sclk"), + CLK_MSR_ID(146, "o_tdmin_b_sclk"), + CLK_MSR_ID(147, "o_tdmin_a_sclk"), + CLK_MSR_ID(148, "o_resampleb_clk"), + CLK_MSR_ID(149, "o_resamplea_clk"), + CLK_MSR_ID(150, "o_pdmb_sysclk"), + CLK_MSR_ID(151, "o_pdmb_dclk"), + CLK_MSR_ID(152, "o_pdm_sysclk"), + CLK_MSR_ID(153, "o_pdm_dclk"), + CLK_MSR_ID(154, "c_alockerb_out_clk"), + CLK_MSR_ID(155, "c_alockerb_in_clk"), + CLK_MSR_ID(156, "c_alocker_out_clk"), + CLK_MSR_ID(157, "c_alocker_in_clk"), + CLK_MSR_ID(158, "audio_mst_clk[34]"), + CLK_MSR_ID(159, "audio_mst_clk[35]"), + CLK_MSR_ID(160, "pwm_n"), + CLK_MSR_ID(161, "pwm_m"), + CLK_MSR_ID(162, "pwm_l"), + CLK_MSR_ID(163, "pwm_k"), + CLK_MSR_ID(164, "pwm_j"), + CLK_MSR_ID(165, "pwm_i"), + CLK_MSR_ID(166, "pwm_h"), + CLK_MSR_ID(167, "pwm_g"), + CLK_MSR_ID(168, "pwm_f"), + CLK_MSR_ID(169, "pwm_e"), + CLK_MSR_ID(170, "pwm_d"), + CLK_MSR_ID(171, "pwm_c"), + CLK_MSR_ID(172, "pwm_b"), + CLK_MSR_ID(173, "pwm_a"), + CLK_MSR_ID(174, "AU_DAC1_CLK_TO_GPIO"), + CLK_MSR_ID(175, "AU_ADC_CLK_TO_GPIO"), + CLK_MSR_ID(176, "rng_ring_osc_clk[0]"), + CLK_MSR_ID(177, "rng_ring_osc_clk[1]"), + CLK_MSR_ID(178, "rng_ring_osc_clk[2]"), + CLK_MSR_ID(179, "rng_ring_osc_clk[3]"), + CLK_MSR_ID(180, "sys_cpu_ring_osc_clk[0]"), + CLK_MSR_ID(181, "sys_cpu_ring_osc_clk[1]"), + CLK_MSR_ID(182, "sys_cpu_ring_osc_clk[2]"), + CLK_MSR_ID(183, "sys_cpu_ring_osc_clk[3]"), + CLK_MSR_ID(184, "sys_cpu_ring_osc_clk[4]"), + CLK_MSR_ID(185, "sys_cpu_ring_osc_clk[5]"), + CLK_MSR_ID(186, "sys_cpu_ring_osc_clk[6]"), + CLK_MSR_ID(187, "sys_cpu_ring_osc_clk[7]"), + CLK_MSR_ID(188, "sys_cpu_ring_osc_clk[8]"), + CLK_MSR_ID(189, "sys_cpu_ring_osc_clk[9]"), + CLK_MSR_ID(190, "sys_cpu_ring_osc_clk[10]"), + CLK_MSR_ID(191, "sys_cpu_ring_osc_clk[11]"), + CLK_MSR_ID(192, "am_ring_osc_clk_out[12](dmc)"), + CLK_MSR_ID(193, "am_ring_osc_clk_out[13](rama)"), + CLK_MSR_ID(194, "am_ring_osc_clk_out[14](nna)"), + CLK_MSR_ID(195, "am_ring_osc_clk_out[15](nna)"), + CLK_MSR_ID(200, "rng_ring_osc_clk_1[0]"), + CLK_MSR_ID(201, "rng_ring_osc_clk_1[1]"), + CLK_MSR_ID(202, "rng_ring_osc_clk_1[2]"), + CLK_MSR_ID(203, "rng_ring_osc_clk_1[3]"), + +}; + +static const struct meson_msr_id clk_msr_s4[] = { + CLK_MSR_ID(0, "sys_clk"), + CLK_MSR_ID(1, "axi_clk"), + CLK_MSR_ID(2, "rtc_clk"), + CLK_MSR_ID(5, "mali"), + CLK_MSR_ID(6, "cpu_clk_div16"), + CLK_MSR_ID(7, "ceca_clk"), + CLK_MSR_ID(8, "cecb_clk"), + CLK_MSR_ID(10, "fclk_div5"), + CLK_MSR_ID(11, "mpll0"), + CLK_MSR_ID(12, "mpll1"), + CLK_MSR_ID(13, "mpll2"), + CLK_MSR_ID(14, "mpll3"), + CLK_MSR_ID(15, "fclk_50m"), + CLK_MSR_ID(16, "pcie_clk_inp"), + CLK_MSR_ID(17, "pcie_clk_inn"), + CLK_MSR_ID(18, "mpll_clk_test_out"), + CLK_MSR_ID(19, "hifi_pll"), + CLK_MSR_ID(20, "gp0_pll"), + CLK_MSR_ID(21, "gp1_pll"), + CLK_MSR_ID(22, "eth_mppll_50m_ckout"), + CLK_MSR_ID(23, "sys_pll_div16"), + CLK_MSR_ID(24, "ddr_dpll_pt_clk"), + CLK_MSR_ID(30, "mod_eth_phy_ref_clk"), + CLK_MSR_ID(31, "mod_eth_tx_clk"), + CLK_MSR_ID(32, "eth_125m"), + CLK_MSR_ID(33, "eth_rmii"), + CLK_MSR_ID(34, "co_clkin_to_mac"), + CLK_MSR_ID(35, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(36, "co_rx_clk"), + CLK_MSR_ID(37, "co_tx_clk"), + CLK_MSR_ID(38, "eth_phy_rxclk"), + CLK_MSR_ID(39, "eth_phy_plltxclk"), + CLK_MSR_ID(40, "ephy_test_clk"), + CLK_MSR_ID(50, "vid_pll_div_clk_out"), + CLK_MSR_ID(51, "enci"), + CLK_MSR_ID(52, "encp"), + CLK_MSR_ID(53, "encl"), + CLK_MSR_ID(54, "vdac"), + CLK_MSR_ID(55, "cdac_clk_c"), + CLK_MSR_ID(56, "mod_tcon_clko"), + CLK_MSR_ID(57, "lcd_an_clk_ph2"), + CLK_MSR_ID(58, "lcd_an_clk_ph3"), + CLK_MSR_ID(59, "hdmitx_pixel"), + CLK_MSR_ID(60, "vdin_meas"), + CLK_MSR_ID(61, "vpu"), + CLK_MSR_ID(62, "vpu_clkb"), + CLK_MSR_ID(63, "vpu_clkb_tmp"), + CLK_MSR_ID(64, "vpu_clkc"), + CLK_MSR_ID(65, "vid_lock"), + CLK_MSR_ID(66, "vapb"), + CLK_MSR_ID(67, "ge2d"), + CLK_MSR_ID(68, "cts_hdcp22_esmclk"), + CLK_MSR_ID(69, "cts_hdcp22_skpclk"), + CLK_MSR_ID(76, "hdmitx_tmds"), + CLK_MSR_ID(77, "hdmitx_sys_clk"), + CLK_MSR_ID(78, "hdmitx_fe_clk"), + CLK_MSR_ID(79, "rama"), + CLK_MSR_ID(93, "vdec"), + CLK_MSR_ID(99, "hevcf"), + CLK_MSR_ID(100, "demod_core"), + CLK_MSR_ID(101, "adc_extclk_in"), + CLK_MSR_ID(102, "cts_demod_core_t2_clk"), + CLK_MSR_ID(103, "adc_dpll_intclk"), + CLK_MSR_ID(104, "adc_dpll_clk_b3"), + CLK_MSR_ID(105, "s2_adc_clk"), + CLK_MSR_ID(106, "deskew_pll_clk_div32_out"), + CLK_MSR_ID(110, "sc"), + CLK_MSR_ID(111, "sar_adc"), + CLK_MSR_ID(113, "sd_emmc_c"), + CLK_MSR_ID(114, "sd_emmc_b"), + CLK_MSR_ID(115, "sd_emmc_a"), + CLK_MSR_ID(116, "gpio_msr_clk"), + CLK_MSR_ID(118, "spicc0"), + CLK_MSR_ID(121, "ts"), + CLK_MSR_ID(130, "audio_vad_clk"), + CLK_MSR_ID(131, "acodec_dac_clk_x128"), + CLK_MSR_ID(132, "audio_locker_in_clk"), + CLK_MSR_ID(133, "audio_locker_out_clk"), + CLK_MSR_ID(134, "audio_tdmout_c_sclk"), + CLK_MSR_ID(135, "audio_tdmout_b_sclk"), + CLK_MSR_ID(136, "audio_tdmout_a_sclk"), + CLK_MSR_ID(137, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(138, "audio_tdmin_c_sclk"), + CLK_MSR_ID(139, "audio_tdmin_b_sclk"), + CLK_MSR_ID(140, "audio_tdmin_a_sclk"), + CLK_MSR_ID(141, "audio_resamplea_clk"), + CLK_MSR_ID(142, "audio_pdm_sysclk"), + CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"), + CLK_MSR_ID(144, "audio_spdifout_mst_clk"), + CLK_MSR_ID(145, "audio_spdifin_mst_clk"), + CLK_MSR_ID(146, "audio_pdm_dclk"), + CLK_MSR_ID(147, "audio_resampleb_clk"), + CLK_MSR_ID(160, "pwm_j"), + CLK_MSR_ID(161, "pwm_i"), + CLK_MSR_ID(162, "pwm_h"), + CLK_MSR_ID(163, "pwm_g"), + CLK_MSR_ID(164, "pwm_f"), + CLK_MSR_ID(165, "pwm_e"), + CLK_MSR_ID(166, "pwm_d"), + CLK_MSR_ID(167, "pwm_c"), + CLK_MSR_ID(168, "pwm_b"), + CLK_MSR_ID(169, "pwm_a"), + CLK_MSR_ID(176, "rng_ring_0"), + CLK_MSR_ID(177, "rng_ring_1"), + CLK_MSR_ID(178, "rng_ring_2"), + CLK_MSR_ID(179, "rng_ring_3"), + CLK_MSR_ID(180, "dmc_osc_ring(LVT16)"), + CLK_MSR_ID(181, "gpu_osc_ring0(LVT16)"), + CLK_MSR_ID(182, "gpu_osc_ring1(ULVT16)"), + CLK_MSR_ID(183, "gpu_osc_ring2(SLVT16)"), + CLK_MSR_ID(184, "vpu_osc_ring0(SVT24)"), + CLK_MSR_ID(185, "vpu_osc_ring1(LVT20)"), + CLK_MSR_ID(186, "vpu_osc_ring2(LVT16)"), + CLK_MSR_ID(187, "dos_osc_ring0(SVT24)"), + CLK_MSR_ID(188, "dos_osc_ring1(SVT16)"), + CLK_MSR_ID(189, "dos_osc_ring2(LVT16)"), + CLK_MSR_ID(190, "dos_osc_ring3(ULVT20)"), + CLK_MSR_ID(192, "axi_sram_osc_ring(SVT16)"), + CLK_MSR_ID(193, "demod_osc_ring0"), + CLK_MSR_ID(194, "demod_osc_ring1"), + CLK_MSR_ID(195, "sar_osc_ring"), + CLK_MSR_ID(196, "sys_cpu_osc_ring0"), + CLK_MSR_ID(197, "sys_cpu_osc_ring1"), + CLK_MSR_ID(198, "sys_cpu_osc_ring2"), + CLK_MSR_ID(199, "sys_cpu_osc_ring3"), + CLK_MSR_ID(200, "sys_cpu_osc_ring4"), + CLK_MSR_ID(201, "sys_cpu_osc_ring5"), + CLK_MSR_ID(202, "sys_cpu_osc_ring6"), + CLK_MSR_ID(203, "sys_cpu_osc_ring7"), + CLK_MSR_ID(204, "sys_cpu_osc_ring8"), + CLK_MSR_ID(205, "sys_cpu_osc_ring9"), + CLK_MSR_ID(206, "sys_cpu_osc_ring10"), + CLK_MSR_ID(207, "sys_cpu_osc_ring11"), + CLK_MSR_ID(208, "sys_cpu_osc_ring12"), + CLK_MSR_ID(209, "sys_cpu_osc_ring13"), + CLK_MSR_ID(210, "sys_cpu_osc_ring14"), + CLK_MSR_ID(211, "sys_cpu_osc_ring15"), + CLK_MSR_ID(212, "sys_cpu_osc_ring16"), + CLK_MSR_ID(213, "sys_cpu_osc_ring17"), + CLK_MSR_ID(214, "sys_cpu_osc_ring18"), + CLK_MSR_ID(215, "sys_cpu_osc_ring19"), + CLK_MSR_ID(216, "sys_cpu_osc_ring20"), + CLK_MSR_ID(217, "sys_cpu_osc_ring21"), + CLK_MSR_ID(218, "sys_cpu_osc_ring22"), + CLK_MSR_ID(219, "sys_cpu_osc_ring23"), + CLK_MSR_ID(220, "sys_cpu_osc_ring24"), + CLK_MSR_ID(221, "sys_cpu_osc_ring25"), + CLK_MSR_ID(222, "sys_cpu_osc_ring26"), + CLK_MSR_ID(223, "sys_cpu_osc_ring27"), + +}; + static int meson_measure_id(struct meson_msr_id *clk_msr_id, - unsigned int duration) + unsigned int duration) { struct meson_msr *priv = clk_msr_id->priv; + const struct msr_reg_offset *reg = priv->data.reg; unsigned int val; int ret; @@ -499,22 +799,22 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id, if (ret) return ret; - regmap_write(priv->regmap, MSR_CLK_REG0, 0); + regmap_write(priv->regmap, reg->freq_ctrl, 0); /* Set measurement duration */ - regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, + regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_DURATION, FIELD_PREP(MSR_DURATION, duration - 1)); /* Set ID */ - regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, + regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_CLK_SRC, FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id)); /* Enable & Start */ - regmap_update_bits(priv->regmap, MSR_CLK_REG0, + regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_RUN | MSR_ENABLE, MSR_RUN | MSR_ENABLE); - ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, + ret = regmap_read_poll_timeout(priv->regmap, reg->freq_ctrl, val, !(val & MSR_BUSY), 10, 10000); if (ret) { mutex_unlock(&measure_lock); @@ -522,10 +822,10 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id, } /* Disable */ - regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); + regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_ENABLE, 0); /* Get the value in multiple of gate time counts */ - regmap_read(priv->regmap, MSR_CLK_REG2, &val); + regmap_read(priv->regmap, reg->freq_val, &val); mutex_unlock(&measure_lock); @@ -573,13 +873,14 @@ DEFINE_SHOW_ATTRIBUTE(clk_msr); static int clk_msr_summary_show(struct seq_file *s, void *data) { struct meson_msr_id *msr_table = s->private; + unsigned int msr_count = msr_table->priv->data.msr_count; unsigned int precision = 0; int val, i; seq_puts(s, " clock rate precision\n"); seq_puts(s, "---------------------------------------------\n"); - for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + for (i = 0 ; i < msr_count ; ++i) { if (!msr_table[i].name) continue; @@ -595,18 +896,18 @@ static int clk_msr_summary_show(struct seq_file *s, void *data) } DEFINE_SHOW_ATTRIBUTE(clk_msr_summary); -static const struct regmap_config meson_clk_msr_regmap_config = { +static struct regmap_config meson_clk_msr_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, - .max_register = MSR_CLK_REG2, }; static int meson_msr_probe(struct platform_device *pdev) { - const struct meson_msr_id *match_data; + const struct meson_msr_data *match_data; struct meson_msr *priv; struct dentry *root, *clks; + struct resource *res; void __iomem *base; int i; @@ -621,60 +922,142 @@ static int meson_msr_probe(struct platform_device *pdev) return -ENODEV; } - memcpy(priv->msr_table, match_data, sizeof(priv->msr_table)); + priv->data.msr_table = devm_kcalloc(&pdev->dev, + match_data->msr_count, + sizeof(struct meson_msr_id), + GFP_KERNEL); + if (!priv->data.msr_table) + return -ENOMEM; - base = devm_platform_ioremap_resource(pdev, 0); + memcpy(priv->data.msr_table, match_data->msr_table, + match_data->msr_count * sizeof(struct meson_msr_id)); + priv->data.msr_count = match_data->msr_count; + + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); + meson_clk_msr_regmap_config.max_register = resource_size(res) - 4; priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &meson_clk_msr_regmap_config); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); + priv->data.reg = devm_kzalloc(&pdev->dev, sizeof(struct msr_reg_offset), + GFP_KERNEL); + if (!priv->data.reg) + return -ENOMEM; + + memcpy((void *)priv->data.reg, match_data->reg, + sizeof(struct msr_reg_offset)); + root = debugfs_create_dir("meson-clk-msr", NULL); clks = debugfs_create_dir("clks", root); debugfs_create_file("measure_summary", 0444, root, - priv->msr_table, &clk_msr_summary_fops); + priv->data.msr_table, &clk_msr_summary_fops); - for (i = 0 ; i < CLK_MSR_MAX ; ++i) { - if (!priv->msr_table[i].name) + for (i = 0 ; i < priv->data.msr_count ; ++i) { + if (!priv->data.msr_table[i].name) continue; - priv->msr_table[i].priv = priv; + priv->data.msr_table[i].priv = priv; - debugfs_create_file(priv->msr_table[i].name, 0444, clks, - &priv->msr_table[i], &clk_msr_fops); + debugfs_create_file(priv->data.msr_table[i].name, 0444, clks, + &priv->data.msr_table[i], &clk_msr_fops); } return 0; } +static const struct msr_reg_offset msr_reg_offset = { + .duty_val = 0x0, + .freq_ctrl = 0x4, + .duty_ctrl = 0x8, + .freq_val = 0xc, +}; + +static const struct meson_msr_data clk_msr_gx_data = { + .msr_table = (void *)clk_msr_gx, + .msr_count = ARRAY_SIZE(clk_msr_gx), + .reg = &msr_reg_offset, +}; + +static const struct meson_msr_data clk_msr_m8_data = { + .msr_table = (void *)clk_msr_m8, + .msr_count = ARRAY_SIZE(clk_msr_m8), + .reg = &msr_reg_offset, +}; + +static const struct meson_msr_data clk_msr_axg_data = { + .msr_table = (void *)clk_msr_axg, + .msr_count = ARRAY_SIZE(clk_msr_axg), + .reg = &msr_reg_offset, +}; + +static const struct meson_msr_data clk_msr_g12a_data = { + .msr_table = (void *)clk_msr_g12a, + .msr_count = ARRAY_SIZE(clk_msr_g12a), + .reg = &msr_reg_offset, +}; + +static const struct meson_msr_data clk_msr_sm1_data = { + .msr_table = (void *)clk_msr_sm1, + .msr_count = ARRAY_SIZE(clk_msr_sm1), + .reg = &msr_reg_offset, +}; + +static const struct msr_reg_offset msr_reg_offset_v2 = { + .freq_ctrl = 0x0, + .duty_ctrl = 0x4, + .freq_val = 0x8, + .duty_val = 0x18, +}; + +static const struct meson_msr_data clk_msr_c3_data = { + .msr_table = (void *)clk_msr_c3, + .msr_count = ARRAY_SIZE(clk_msr_c3), + .reg = &msr_reg_offset_v2, +}; + +static const struct meson_msr_data clk_msr_s4_data = { + .msr_table = (void *)clk_msr_s4, + .msr_count = ARRAY_SIZE(clk_msr_s4), + .reg = &msr_reg_offset_v2, +}; + static const struct of_device_id meson_msr_match_table[] = { { .compatible = "amlogic,meson-gx-clk-measure", - .data = (void *)clk_msr_gx, + .data = &clk_msr_gx_data, }, { .compatible = "amlogic,meson8-clk-measure", - .data = (void *)clk_msr_m8, + .data = &clk_msr_m8_data, }, { .compatible = "amlogic,meson8b-clk-measure", - .data = (void *)clk_msr_m8, + .data = &clk_msr_m8_data, }, { .compatible = "amlogic,meson-axg-clk-measure", - .data = (void *)clk_msr_axg, + .data = &clk_msr_axg_data, }, { .compatible = "amlogic,meson-g12a-clk-measure", - .data = (void *)clk_msr_g12a, + .data = &clk_msr_g12a_data, }, { .compatible = "amlogic,meson-sm1-clk-measure", - .data = (void *)clk_msr_sm1, + .data = &clk_msr_sm1_data, + }, + { + .compatible = "amlogic,c3-clk-measure", + .data = &clk_msr_c3_data, + }, + { + .compatible = "amlogic,s4-clk-measure", + .data = &clk_msr_s4_data, }, { /* sentinel */ } }; diff --git a/drivers/soc/apple/rtkit-internal.h b/drivers/soc/apple/rtkit-internal.h index 27c9fa745fd5..b8d5244678f0 100644 --- a/drivers/soc/apple/rtkit-internal.h +++ b/drivers/soc/apple/rtkit-internal.h @@ -44,6 +44,7 @@ struct apple_rtkit { struct apple_rtkit_shmem ioreport_buffer; struct apple_rtkit_shmem crashlog_buffer; + struct apple_rtkit_shmem oslog_buffer; struct apple_rtkit_shmem syslog_buffer; char *syslog_msg_buffer; diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index e6d940292c9f..5fffd0f003dc 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -12,6 +12,7 @@ enum { APPLE_RTKIT_PWR_STATE_IDLE = 0x201, /* sleeping, retain state */ APPLE_RTKIT_PWR_STATE_QUIESCED = 0x10, /* running but no communication */ APPLE_RTKIT_PWR_STATE_ON = 0x20, /* normal operating state */ + APPLE_RTKIT_PWR_STATE_INIT = 0x220, /* init after starting the coproc */ }; enum { @@ -66,8 +67,9 @@ enum { #define APPLE_RTKIT_SYSLOG_MSG_SIZE GENMASK_ULL(31, 24) #define APPLE_RTKIT_OSLOG_TYPE GENMASK_ULL(63, 56) -#define APPLE_RTKIT_OSLOG_INIT 1 -#define APPLE_RTKIT_OSLOG_ACK 3 +#define APPLE_RTKIT_OSLOG_BUFFER_REQUEST 1 +#define APPLE_RTKIT_OSLOG_SIZE GENMASK_ULL(55, 36) +#define APPLE_RTKIT_OSLOG_IOVA GENMASK_ULL(35, 0) #define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11 #define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12 @@ -97,12 +99,19 @@ bool apple_rtkit_is_crashed(struct apple_rtkit *rtk) } EXPORT_SYMBOL_GPL(apple_rtkit_is_crashed); -static void apple_rtkit_management_send(struct apple_rtkit *rtk, u8 type, +static int apple_rtkit_management_send(struct apple_rtkit *rtk, u8 type, u64 msg) { + int ret; + msg &= ~APPLE_RTKIT_MGMT_TYPE; msg |= FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, type); - apple_rtkit_send_message(rtk, APPLE_RTKIT_EP_MGMT, msg, NULL, false); + ret = apple_rtkit_send_message(rtk, APPLE_RTKIT_EP_MGMT, msg, NULL, false); + + if (ret) + dev_err(rtk->dev, "RTKit: Failed to send management message: %d\n", ret); + + return ret; } static void apple_rtkit_management_rx_hello(struct apple_rtkit *rtk, u64 msg) @@ -251,15 +260,21 @@ static int apple_rtkit_common_rx_get_buffer(struct apple_rtkit *rtk, struct apple_rtkit_shmem *buffer, u8 ep, u64 msg) { - size_t n_4kpages = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg); u64 reply; int err; + /* The different size vs. IOVA shifts look odd but are indeed correct this way */ + if (ep == APPLE_RTKIT_EP_OSLOG) { + buffer->size = FIELD_GET(APPLE_RTKIT_OSLOG_SIZE, msg); + buffer->iova = FIELD_GET(APPLE_RTKIT_OSLOG_IOVA, msg) << 12; + } else { + buffer->size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg) << 12; + buffer->iova = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg); + } + buffer->buffer = NULL; buffer->iomem = NULL; buffer->is_mapped = false; - buffer->iova = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg); - buffer->size = n_4kpages << 12; dev_dbg(rtk->dev, "RTKit: buffer request for 0x%zx bytes at %pad\n", buffer->size, &buffer->iova); @@ -284,17 +299,30 @@ static int apple_rtkit_common_rx_get_buffer(struct apple_rtkit *rtk, } if (!buffer->is_mapped) { - reply = FIELD_PREP(APPLE_RTKIT_SYSLOG_TYPE, - APPLE_RTKIT_BUFFER_REQUEST); - reply |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, n_4kpages); - reply |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, - buffer->iova); + /* oslog uses different fields and needs a shifted IOVA instead of size */ + if (ep == APPLE_RTKIT_EP_OSLOG) { + reply = FIELD_PREP(APPLE_RTKIT_OSLOG_TYPE, + APPLE_RTKIT_OSLOG_BUFFER_REQUEST); + reply |= FIELD_PREP(APPLE_RTKIT_OSLOG_SIZE, buffer->size); + reply |= FIELD_PREP(APPLE_RTKIT_OSLOG_IOVA, + buffer->iova >> 12); + } else { + reply = FIELD_PREP(APPLE_RTKIT_SYSLOG_TYPE, + APPLE_RTKIT_BUFFER_REQUEST); + reply |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, + buffer->size >> 12); + reply |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, + buffer->iova); + } apple_rtkit_send_message(rtk, ep, reply, NULL, false); } return 0; error: + dev_err(rtk->dev, "RTKit: failed buffer request for 0x%zx bytes (%d)\n", + buffer->size, err); + buffer->buffer = NULL; buffer->iomem = NULL; buffer->iova = 0; @@ -360,7 +388,6 @@ static void apple_rtkit_crashlog_rx(struct apple_rtkit *rtk, u64 msg) apple_rtkit_memcpy(rtk, bfr, &rtk->crashlog_buffer, 0, rtk->crashlog_buffer.size); apple_rtkit_crashlog_dump(rtk, bfr, rtk->crashlog_buffer.size); - kfree(bfr); } else { dev_err(rtk->dev, "RTKit: Couldn't allocate crashlog shadow buffer\n"); @@ -368,7 +395,9 @@ static void apple_rtkit_crashlog_rx(struct apple_rtkit *rtk, u64 msg) rtk->crashed = true; if (rtk->ops->crashed) - rtk->ops->crashed(rtk->cookie); + rtk->ops->crashed(rtk->cookie, bfr, rtk->crashlog_buffer.size); + + kfree(bfr); } static void apple_rtkit_ioreport_rx(struct apple_rtkit *rtk, u64 msg) @@ -448,7 +477,7 @@ static void apple_rtkit_syslog_rx_log(struct apple_rtkit *rtk, u64 msg) log_context[sizeof(log_context) - 1] = 0; - msglen = rtk->syslog_msg_size - 1; + msglen = strnlen(rtk->syslog_msg_buffer, rtk->syslog_msg_size - 1); while (msglen > 0 && should_crop_syslog_char(rtk->syslog_msg_buffer[msglen - 1])) msglen--; @@ -482,25 +511,18 @@ static void apple_rtkit_syslog_rx(struct apple_rtkit *rtk, u64 msg) } } -static void apple_rtkit_oslog_rx_init(struct apple_rtkit *rtk, u64 msg) -{ - u64 ack; - - dev_dbg(rtk->dev, "RTKit: oslog init: msg: 0x%llx\n", msg); - ack = FIELD_PREP(APPLE_RTKIT_OSLOG_TYPE, APPLE_RTKIT_OSLOG_ACK); - apple_rtkit_send_message(rtk, APPLE_RTKIT_EP_OSLOG, ack, NULL, false); -} - static void apple_rtkit_oslog_rx(struct apple_rtkit *rtk, u64 msg) { u8 type = FIELD_GET(APPLE_RTKIT_OSLOG_TYPE, msg); switch (type) { - case APPLE_RTKIT_OSLOG_INIT: - apple_rtkit_oslog_rx_init(rtk, msg); + case APPLE_RTKIT_OSLOG_BUFFER_REQUEST: + apple_rtkit_common_rx_get_buffer(rtk, &rtk->oslog_buffer, + APPLE_RTKIT_EP_OSLOG, msg); break; default: - dev_warn(rtk->dev, "RTKit: Unknown oslog message: %llx\n", msg); + dev_warn(rtk->dev, "RTKit: Unknown oslog message: %llx\n", + msg); } } @@ -588,11 +610,18 @@ int apple_rtkit_send_message(struct apple_rtkit *rtk, u8 ep, u64 message, .msg1 = ep, }; - if (rtk->crashed) + if (rtk->crashed) { + dev_warn(rtk->dev, + "RTKit: Device is crashed, cannot send message\n"); return -EINVAL; + } + if (ep >= APPLE_RTKIT_APP_ENDPOINT_START && - !apple_rtkit_is_running(rtk)) + !apple_rtkit_is_running(rtk)) { + dev_warn(rtk->dev, + "RTKit: Endpoint 0x%02x is not running, cannot send message\n", ep); return -EINVAL; + } /* * The message will be sent with a MMIO write. We need the barrier @@ -667,7 +696,7 @@ struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, rtk->mbox->rx = apple_rtkit_rx; rtk->mbox->cookie = rtk; - rtk->wq = alloc_ordered_workqueue("rtkit-%s", WQ_MEM_RECLAIM, + rtk->wq = alloc_ordered_workqueue("rtkit-%s", WQ_HIGHPRI | WQ_MEM_RECLAIM, dev_name(rtk->dev)); if (!rtk->wq) { ret = -ENOMEM; @@ -710,6 +739,7 @@ int apple_rtkit_reinit(struct apple_rtkit *rtk) apple_rtkit_free_buffer(rtk, &rtk->ioreport_buffer); apple_rtkit_free_buffer(rtk, &rtk->crashlog_buffer); + apple_rtkit_free_buffer(rtk, &rtk->oslog_buffer); apple_rtkit_free_buffer(rtk, &rtk->syslog_buffer); kfree(rtk->syslog_msg_buffer); @@ -742,8 +772,10 @@ static int apple_rtkit_set_ap_power_state(struct apple_rtkit *rtk, reinit_completion(&rtk->ap_pwr_ack_completion); msg = FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, state); - apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_AP_PWR_STATE, - msg); + ret = apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_AP_PWR_STATE, + msg); + if (ret) + return ret; ret = apple_rtkit_wait_for_completion(&rtk->ap_pwr_ack_completion); if (ret) @@ -763,8 +795,10 @@ static int apple_rtkit_set_iop_power_state(struct apple_rtkit *rtk, reinit_completion(&rtk->iop_pwr_ack_completion); msg = FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, state); - apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE, - msg); + ret = apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE, + msg); + if (ret) + return ret; ret = apple_rtkit_wait_for_completion(&rtk->iop_pwr_ack_completion); if (ret) @@ -865,6 +899,7 @@ EXPORT_SYMBOL_GPL(apple_rtkit_quiesce); int apple_rtkit_wake(struct apple_rtkit *rtk) { u64 msg; + int ret; if (apple_rtkit_is_running(rtk)) return -EINVAL; @@ -875,9 +910,11 @@ int apple_rtkit_wake(struct apple_rtkit *rtk) * Use open-coded apple_rtkit_set_iop_power_state since apple_rtkit_boot * will wait for the completion anyway. */ - msg = FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON); - apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE, - msg); + msg = FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_INIT); + ret = apple_rtkit_management_send(rtk, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE, + msg); + if (ret) + return ret; return apple_rtkit_boot(rtk); } @@ -890,6 +927,7 @@ void apple_rtkit_free(struct apple_rtkit *rtk) apple_rtkit_free_buffer(rtk, &rtk->ioreport_buffer); apple_rtkit_free_buffer(rtk, &rtk->crashlog_buffer); + apple_rtkit_free_buffer(rtk, &rtk->oslog_buffer); apple_rtkit_free_buffer(rtk, &rtk->syslog_buffer); kfree(rtk->syslog_msg_buffer); diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c index 9ab5ba9cf1d6..ef8f355589a5 100644 --- a/drivers/soc/aspeed/aspeed-lpc-snoop.c +++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c @@ -166,7 +166,7 @@ static int aspeed_lpc_snoop_config_irq(struct aspeed_lpc_snoop *lpc_snoop, int rc; lpc_snoop->irq = platform_get_irq(pdev, 0); - if (!lpc_snoop->irq) + if (lpc_snoop->irq < 0) return -ENODEV; rc = devm_request_irq(dev, lpc_snoop->irq, @@ -200,11 +200,15 @@ static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop, lpc_snoop->chan[channel].miscdev.minor = MISC_DYNAMIC_MINOR; lpc_snoop->chan[channel].miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DEVICE_NAME, channel); + if (!lpc_snoop->chan[channel].miscdev.name) { + rc = -ENOMEM; + goto err_free_fifo; + } lpc_snoop->chan[channel].miscdev.fops = &snoop_fops; lpc_snoop->chan[channel].miscdev.parent = dev; rc = misc_register(&lpc_snoop->chan[channel].miscdev); if (rc) - return rc; + goto err_free_fifo; /* Enable LPC snoop channel at requested port */ switch (channel) { @@ -221,7 +225,8 @@ static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop, hicrb_en = HICRB_ENSNP1D; break; default: - return -EINVAL; + rc = -EINVAL; + goto err_misc_deregister; } regmap_update_bits(lpc_snoop->regmap, HICR5, hicr5_en, hicr5_en); @@ -231,6 +236,12 @@ static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop, regmap_update_bits(lpc_snoop->regmap, HICRB, hicrb_en, hicrb_en); + return 0; + +err_misc_deregister: + misc_deregister(&lpc_snoop->chan[channel].miscdev); +err_free_fifo: + kfifo_free(&lpc_snoop->chan[channel].fifo); return rc; } diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 298b542dd1c0..09347bccdb1d 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -246,6 +246,9 @@ static const struct at91_soc socs[] __initconst = { "samv70q19", "samv7"), #endif #ifdef CONFIG_SOC_SAMA7 + AT91_SOC(SAMA7D65_CIDR_MATCH, AT91_CIDR_MASK_SAMA7G5, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7D65_EXID_MATCH, + "sama7d65", "sama7d6"), AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, "sama7g51", "sama7g5"), @@ -305,6 +308,7 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) void __iomem *regs; static const struct of_device_id chipids[] = { { .compatible = "atmel,sama5d2-chipid" }, + { .compatible = "microchip,sama7d65-chipid" }, { .compatible = "microchip,sama7g5-chipid" }, { }, }; @@ -393,6 +397,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = { { .compatible = "atmel,at91sam9", }, { .compatible = "atmel,sama5", }, { .compatible = "atmel,samv7", }, + { .compatible = "microchip,sama7d65", }, { .compatible = "microchip,sama7g5", }, { } }; diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 2c78e54255f7..66a74017d9a3 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAM9X7_CIDR_MATCH 0x09750020 +#define SAMA7D65_CIDR_MATCH 0x00262100 #define SAMA7G5_CIDR_MATCH 0x00162100 #define AT91SAM9M11_EXID_MATCH 0x00000001 @@ -75,6 +76,8 @@ at91_soc_init(const struct at91_soc *socs); #define SAM9X75_D5M_EXID_MATCH 0x00000010 #define SAM9X75_EXID_MATCH 0x00000000 +#define SAMA7D65_EXID_MATCH 0x00000080 + #define SAMA7G51_EXID_MATCH 0x3 #define SAMA7G52_EXID_MATCH 0x2 #define SAMA7G53_EXID_MATCH 0x1 diff --git a/drivers/soc/dove/pmu.c b/drivers/soc/dove/pmu.c index 6202dbcd20a8..7bbd3f940e4d 100644 --- a/drivers/soc/dove/pmu.c +++ b/drivers/soc/dove/pmu.c @@ -257,10 +257,9 @@ static void pmu_irq_handler(struct irq_desc *desc) * So, let's structure the code so that the window is as small as * possible. */ - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); done &= readl_relaxed(base + PMC_IRQ_CAUSE); writel_relaxed(done, base + PMC_IRQ_CAUSE); - irq_gc_unlock(gc); } static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) @@ -274,8 +273,8 @@ static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) writel(0, pmu->pmc_base + PMC_IRQ_MASK); writel(0, pmu->pmc_base + PMC_IRQ_CAUSE); - domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS, - &irq_generic_chip_ops, NULL); + domain = irq_domain_create_linear(of_fwnode_handle(pmu->of_node), NR_PMU_IRQS, + &irq_generic_chip_ops, NULL); if (!domain) { pr_err("%s: unable to add irq domain\n", name); return -ENOMEM; diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig index a1e0bc8c1757..47870e29c290 100644 --- a/drivers/soc/fsl/Kconfig +++ b/drivers/soc/fsl/Kconfig @@ -36,7 +36,7 @@ config FSL_MC_DPIO config DPAA2_CONSOLE tristate "QorIQ DPAA2 console driver" depends on OF && (ARCH_LAYERSCAPE || COMPILE_TEST) - default y + default ARCH_LAYERSCAPE help Console driver for DPAA2 platforms. Exports 2 char devices, /dev/dpaa2_mc_console and /dev/dpaa2_aiop_console, diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c index 4dc8aba33d9b..9be240999f87 100644 --- a/drivers/soc/fsl/qbman/qman.c +++ b/drivers/soc/fsl/qbman/qman.c @@ -1270,7 +1270,7 @@ static int qman_create_portal(struct qman_portal *portal, qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH); qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH); qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD); - portal->cgrs = kmalloc_array(2, sizeof(*cgrs), GFP_KERNEL); + portal->cgrs = kmalloc_array(2, sizeof(*portal->cgrs), GFP_KERNEL); if (!portal->cgrs) goto fail_cgrs; /* initial snapshot is no-depletion */ diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c index bbae3d39c7be..4068b501a3a3 100644 --- a/drivers/soc/fsl/qe/qe_ic.c +++ b/drivers/soc/fsl/qe/qe_ic.c @@ -232,11 +232,6 @@ static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg, iowrite32be(value, base + (reg >> 2)); } -static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) -{ - return irq_get_chip_data(virq); -} - static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) { return irq_data_get_irq_chip_data(d); @@ -344,7 +339,7 @@ static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) if (irq == 0) return 0; - return irq_linear_revmap(qe_ic->irqhost, irq); + return irq_find_mapping(qe_ic->irqhost, irq); } /* Return an interrupt vector or 0 if no interrupt is pending. */ @@ -360,7 +355,7 @@ static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) if (irq == 0) return 0; - return irq_linear_revmap(qe_ic->irqhost, irq); + return irq_find_mapping(qe_ic->irqhost, irq); } static void qe_ic_cascade_low(struct irq_desc *desc) @@ -446,8 +441,8 @@ static int qe_ic_init(struct platform_device *pdev) high_handler = NULL; } - qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, - &qe_ic_host_ops, qe_ic); + qe_ic->irqhost = irq_domain_create_linear(of_fwnode_handle(node), NR_QE_IC_INTS, + &qe_ic_host_ops, qe_ic); if (qe_ic->irqhost == NULL) { dev_err(dev, "failed to add irq domain\n"); return -ENODEV; @@ -455,13 +450,11 @@ static int qe_ic_init(struct platform_device *pdev) qe_ic_write(qe_ic->regs, QEIC_CICR, 0); - irq_set_handler_data(qe_ic->virq_low, qe_ic); - irq_set_chained_handler(qe_ic->virq_low, low_handler); + irq_set_chained_handler_and_data(qe_ic->virq_low, low_handler, qe_ic); - if (high_handler) { - irq_set_handler_data(qe_ic->virq_high, qe_ic); - irq_set_chained_handler(qe_ic->virq_high, high_handler); - } + if (high_handler) + irq_set_chained_handler_and_data(qe_ic->virq_high, + high_handler, qe_ic); return 0; } static const struct of_device_id qe_ic_ids[] = { diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c index 8aa8dec14911..7fc353732d55 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.c +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -167,10 +167,6 @@ static void hccs_pcc_rx_callback(struct mbox_client *cl, void *mssg) static void hccs_unregister_pcc_channel(struct hccs_dev *hdev) { - struct hccs_mbox_client_info *cl_info = &hdev->cl_info; - - if (cl_info->pcc_comm_addr) - iounmap(cl_info->pcc_comm_addr); pcc_mbox_free_channel(hdev->cl_info.pcc_chan); } @@ -179,6 +175,7 @@ static int hccs_register_pcc_channel(struct hccs_dev *hdev) struct hccs_mbox_client_info *cl_info = &hdev->cl_info; struct mbox_client *cl = &cl_info->client; struct pcc_mbox_chan *pcc_chan; + struct mbox_chan *mbox_chan; struct device *dev = hdev->dev; int rc; @@ -196,7 +193,7 @@ static int hccs_register_pcc_channel(struct hccs_dev *hdev) goto out; } cl_info->pcc_chan = pcc_chan; - cl_info->mbox_chan = pcc_chan->mchan; + mbox_chan = pcc_chan->mchan; /* * pcc_chan->latency is just a nominal value. In reality the remote @@ -206,34 +203,24 @@ static int hccs_register_pcc_channel(struct hccs_dev *hdev) cl_info->deadline_us = HCCS_PCC_CMD_WAIT_RETRIES_NUM * pcc_chan->latency; if (!hdev->verspec_data->has_txdone_irq && - cl_info->mbox_chan->mbox->txdone_irq) { + mbox_chan->mbox->txdone_irq) { dev_err(dev, "PCC IRQ in PCCT is enabled.\n"); rc = -EINVAL; goto err_mbx_channel_free; } else if (hdev->verspec_data->has_txdone_irq && - !cl_info->mbox_chan->mbox->txdone_irq) { + !mbox_chan->mbox->txdone_irq) { dev_err(dev, "PCC IRQ in PCCT isn't supported.\n"); rc = -EINVAL; goto err_mbx_channel_free; } - if (!pcc_chan->shmem_base_addr || - pcc_chan->shmem_size != HCCS_PCC_SHARE_MEM_BYTES) { - dev_err(dev, "The base address or size (%llu) of PCC communication region is invalid.\n", - pcc_chan->shmem_size); + if (pcc_chan->shmem_size != HCCS_PCC_SHARE_MEM_BYTES) { + dev_err(dev, "Base size (%llu) of PCC communication region must be %d bytes.\n", + pcc_chan->shmem_size, HCCS_PCC_SHARE_MEM_BYTES); rc = -EINVAL; goto err_mbx_channel_free; } - cl_info->pcc_comm_addr = ioremap(pcc_chan->shmem_base_addr, - pcc_chan->shmem_size); - if (!cl_info->pcc_comm_addr) { - dev_err(dev, "Failed to ioremap PCC communication region for channel-%u.\n", - hdev->chan_id); - rc = -ENOMEM; - goto err_mbx_channel_free; - } - return 0; err_mbx_channel_free: @@ -246,7 +233,7 @@ static int hccs_wait_cmd_complete_by_poll(struct hccs_dev *hdev) { struct hccs_mbox_client_info *cl_info = &hdev->cl_info; struct acpi_pcct_shared_memory __iomem *comm_base = - cl_info->pcc_comm_addr; + cl_info->pcc_chan->shmem; u16 status; int ret; @@ -289,7 +276,7 @@ static inline void hccs_fill_pcc_shared_mem_region(struct hccs_dev *hdev, .status = 0, }; - memcpy_toio(hdev->cl_info.pcc_comm_addr, (void *)&tmp, + memcpy_toio(hdev->cl_info.pcc_chan->shmem, (void *)&tmp, sizeof(struct acpi_pcct_shared_memory)); /* Copy the message to the PCC comm space */ @@ -309,7 +296,7 @@ static inline void hccs_fill_ext_pcc_shared_mem_region(struct hccs_dev *hdev, .command = cmd, }; - memcpy_toio(hdev->cl_info.pcc_comm_addr, (void *)&tmp, + memcpy_toio(hdev->cl_info.pcc_chan->shmem, (void *)&tmp, sizeof(struct acpi_pcct_ext_pcc_shared_memory)); /* Copy the message to the PCC comm space */ @@ -321,12 +308,13 @@ static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, { const struct hccs_verspecific_data *verspec_data = hdev->verspec_data; struct hccs_mbox_client_info *cl_info = &hdev->cl_info; + struct mbox_chan *mbox_chan = cl_info->pcc_chan->mchan; struct hccs_fw_inner_head *fw_inner_head; void __iomem *comm_space; u16 space_size; int ret; - comm_space = cl_info->pcc_comm_addr + verspec_data->shared_mem_size; + comm_space = cl_info->pcc_chan->shmem + verspec_data->shared_mem_size; space_size = HCCS_PCC_SHARE_MEM_BYTES - verspec_data->shared_mem_size; verspec_data->fill_pcc_shared_mem(hdev, cmd, desc, comm_space, space_size); @@ -334,7 +322,7 @@ static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, reinit_completion(&cl_info->done); /* Ring doorbell */ - ret = mbox_send_message(cl_info->mbox_chan, &cmd); + ret = mbox_send_message(mbox_chan, &cmd); if (ret < 0) { dev_err(hdev->dev, "Send PCC mbox message failed, ret = %d.\n", ret); @@ -356,9 +344,9 @@ static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, end: if (verspec_data->has_txdone_irq) - mbox_chan_txdone(cl_info->mbox_chan, ret); + mbox_chan_txdone(mbox_chan, ret); else - mbox_client_txdone(cl_info->mbox_chan, ret); + mbox_client_txdone(mbox_chan, ret); return ret; } @@ -1539,8 +1527,8 @@ static ssize_t used_types_show(struct kobject *kobj, u16 i; for (i = 0; i < hdev->used_type_num - 1; i++) - len += sysfs_emit(&buf[len], "%s ", hdev->type_name_maps[i].name); - len += sysfs_emit(&buf[len], "%s\n", hdev->type_name_maps[i].name); + len += sysfs_emit_at(buf, len, "%s ", hdev->type_name_maps[i].name); + len += sysfs_emit_at(buf, len, "%s\n", hdev->type_name_maps[i].name); return len; } diff --git a/drivers/soc/hisilicon/kunpeng_hccs.h b/drivers/soc/hisilicon/kunpeng_hccs.h index dc267136919b..f0a9a5618d97 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.h +++ b/drivers/soc/hisilicon/kunpeng_hccs.h @@ -60,10 +60,8 @@ struct hccs_chip_info { struct hccs_mbox_client_info { struct mbox_client client; - struct mbox_chan *mbox_chan; struct pcc_mbox_chan *pcc_chan; u64 deadline_us; - void __iomem *pcc_comm_addr; struct completion done; }; diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c index 8ac7658e3d52..04a1b60f2f2b 100644 --- a/drivers/soc/imx/soc-imx8m.c +++ b/drivers/soc/imx/soc-imx8m.c @@ -24,13 +24,21 @@ #define OCOTP_UID_HIGH 0x420 #define IMX8MP_OCOTP_UID_OFFSET 0x10 +#define IMX8MP_OCOTP_UID_HIGH 0xE00 /* Same as ANADIG_DIGPROG_IMX7D */ #define ANADIG_DIGPROG_IMX8MM 0x800 struct imx8_soc_data { char *name; - int (*soc_revision)(u32 *socrev, u64 *socuid); + const char *ocotp_compatible; + int (*soc_revision)(struct platform_device *pdev, u32 *socrev); + int (*soc_uid)(struct platform_device *pdev, u64 *socuid); +}; + +struct imx8_soc_drvdata { + void __iomem *ocotp_base; + struct clk *clk; }; #ifdef CONFIG_HAVE_ARM_SMCCC @@ -49,30 +57,24 @@ static u32 imx8mq_soc_revision_from_atf(void) static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; }; #endif -static int imx8mq_soc_revision(u32 *socrev, u64 *socuid) +static int imx8m_soc_uid(struct platform_device *pdev, u64 *socuid) { - struct device_node *np __free(device_node) = - of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); - void __iomem *ocotp_base; - u32 magic; - u32 rev; - struct clk *clk; - int ret; - - if (!np) - return -EINVAL; + struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev); + void __iomem *ocotp_base = drvdata->ocotp_base; - ocotp_base = of_iomap(np, 0); - if (!ocotp_base) - return -EINVAL; + *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); + *socuid <<= 32; + *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); - clk = of_clk_get_by_name(np, NULL); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - goto err_clk; - } + return 0; +} - clk_prepare_enable(clk); +static int imx8mq_soc_revision(struct platform_device *pdev, u32 *socrev) +{ + struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev); + void __iomem *ocotp_base = drvdata->ocotp_base; + u32 magic; + u32 rev; /* * SOC revision on older imx8mq is not available in fuses so query @@ -85,98 +87,109 @@ static int imx8mq_soc_revision(u32 *socrev, u64 *socuid) rev = REV_B1; } - *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); - *socuid <<= 32; - *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); - *socrev = rev; - clk_disable_unprepare(clk); - clk_put(clk); - iounmap(ocotp_base); - return 0; +} -err_clk: - iounmap(ocotp_base); - return ret; +static int imx8mp_soc_uid(struct platform_device *pdev, u64 *socuid) +{ + struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev); + void __iomem *ocotp_base = drvdata->ocotp_base; + + socuid[0] = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + IMX8MP_OCOTP_UID_OFFSET); + socuid[0] <<= 32; + socuid[0] |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + IMX8MP_OCOTP_UID_OFFSET); + + socuid[1] = readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH + 0x10); + socuid[1] <<= 32; + socuid[1] |= readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH); + + return 0; } -static int imx8mm_soc_uid(u64 *socuid) +static int imx8mm_soc_revision(struct platform_device *pdev, u32 *socrev) { struct device_node *np __free(device_node) = - of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); - void __iomem *ocotp_base; - struct clk *clk; - int ret = 0; - u32 offset = of_machine_is_compatible("fsl,imx8mp") ? - IMX8MP_OCOTP_UID_OFFSET : 0; + of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); + void __iomem *anatop_base; if (!np) return -EINVAL; - ocotp_base = of_iomap(np, 0); - if (!ocotp_base) + anatop_base = of_iomap(np, 0); + if (!anatop_base) return -EINVAL; - clk = of_clk_get_by_name(np, NULL); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - goto err_clk; - } - - clk_prepare_enable(clk); - - *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset); - *socuid <<= 32; - *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset); + *socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); - clk_disable_unprepare(clk); - clk_put(clk); + iounmap(anatop_base); -err_clk: - iounmap(ocotp_base); - return ret; + return 0; } -static int imx8mm_soc_revision(u32 *socrev, u64 *socuid) +static int imx8m_soc_prepare(struct platform_device *pdev, const char *ocotp_compatible) { struct device_node *np __free(device_node) = - of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); - void __iomem *anatop_base; + of_find_compatible_node(NULL, NULL, ocotp_compatible); + struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev); + int ret = 0; if (!np) return -EINVAL; - anatop_base = of_iomap(np, 0); - if (!anatop_base) + drvdata->ocotp_base = of_iomap(np, 0); + if (!drvdata->ocotp_base) return -EINVAL; - *socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); + drvdata->clk = of_clk_get_by_name(np, NULL); + if (IS_ERR(drvdata->clk)) { + ret = PTR_ERR(drvdata->clk); + goto err_clk; + } - iounmap(anatop_base); + return clk_prepare_enable(drvdata->clk); - return imx8mm_soc_uid(socuid); +err_clk: + iounmap(drvdata->ocotp_base); + return ret; +} + +static void imx8m_soc_unprepare(struct platform_device *pdev) +{ + struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev); + + clk_disable_unprepare(drvdata->clk); + clk_put(drvdata->clk); + iounmap(drvdata->ocotp_base); } static const struct imx8_soc_data imx8mq_soc_data = { .name = "i.MX8MQ", + .ocotp_compatible = "fsl,imx8mq-ocotp", .soc_revision = imx8mq_soc_revision, + .soc_uid = imx8m_soc_uid, }; static const struct imx8_soc_data imx8mm_soc_data = { .name = "i.MX8MM", + .ocotp_compatible = "fsl,imx8mm-ocotp", .soc_revision = imx8mm_soc_revision, + .soc_uid = imx8m_soc_uid, }; static const struct imx8_soc_data imx8mn_soc_data = { .name = "i.MX8MN", + .ocotp_compatible = "fsl,imx8mm-ocotp", .soc_revision = imx8mm_soc_revision, + .soc_uid = imx8m_soc_uid, }; static const struct imx8_soc_data imx8mp_soc_data = { .name = "i.MX8MP", + .ocotp_compatible = "fsl,imx8mm-ocotp", .soc_revision = imx8mm_soc_revision, + .soc_uid = imx8mp_soc_uid, }; static __maybe_unused const struct of_device_id imx8_soc_match[] = { @@ -192,21 +205,39 @@ static __maybe_unused const struct of_device_id imx8_soc_match[] = { devm_kasprintf((dev), GFP_KERNEL, "%d.%d", ((soc_rev) >> 4) & 0xf, (soc_rev) & 0xf) : \ "unknown" +static void imx8m_unregister_soc(void *data) +{ + soc_device_unregister(data); +} + +static void imx8m_unregister_cpufreq(void *data) +{ + platform_device_unregister(data); +} + static int imx8m_soc_probe(struct platform_device *pdev) { struct soc_device_attribute *soc_dev_attr; + struct platform_device *cpufreq_dev; const struct imx8_soc_data *data; + struct imx8_soc_drvdata *drvdata; struct device *dev = &pdev->dev; const struct of_device_id *id; struct soc_device *soc_dev; u32 soc_rev = 0; - u64 soc_uid = 0; + u64 soc_uid[2] = {0, 0}; int ret; soc_dev_attr = devm_kzalloc(dev, sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) return -ENOMEM; + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + platform_set_drvdata(pdev, drvdata); + soc_dev_attr->family = "Freescale i.MX"; ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); @@ -220,18 +251,37 @@ static int imx8m_soc_probe(struct platform_device *pdev) data = id->data; if (data) { soc_dev_attr->soc_id = data->name; + ret = imx8m_soc_prepare(pdev, data->ocotp_compatible); + if (ret) + return ret; + if (data->soc_revision) { - ret = data->soc_revision(&soc_rev, &soc_uid); - if (ret) + ret = data->soc_revision(pdev, &soc_rev); + if (ret) { + imx8m_soc_unprepare(pdev); + return ret; + } + } + if (data->soc_uid) { + ret = data->soc_uid(pdev, soc_uid); + if (ret) { + imx8m_soc_unprepare(pdev); return ret; + } } + imx8m_soc_unprepare(pdev); } soc_dev_attr->revision = imx8_revision(dev, soc_rev); if (!soc_dev_attr->revision) return -ENOMEM; - soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX", soc_uid); + if (soc_uid[1]) + soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX%016llX", + soc_uid[1], soc_uid[0]); + else + soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX", + soc_uid[0]); if (!soc_dev_attr->serial_number) return -ENOMEM; @@ -239,11 +289,22 @@ static int imx8m_soc_probe(struct platform_device *pdev) if (IS_ERR(soc_dev)) return PTR_ERR(soc_dev); + ret = devm_add_action(dev, imx8m_unregister_soc, soc_dev); + if (ret) + return ret; + pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id, soc_dev_attr->revision); - if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) - platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); + if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) { + cpufreq_dev = platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); + if (IS_ERR(cpufreq_dev)) + return dev_err_probe(dev, PTR_ERR(cpufreq_dev), + "Failed to register imx-cpufreq-dev device\n"); + ret = devm_add_action(dev, imx8m_unregister_cpufreq, cpufreq_dev); + if (ret) + return ret; + } return 0; } diff --git a/drivers/soc/loongson/loongson2_guts.c b/drivers/soc/loongson/loongson2_guts.c index ae42e3a9127f..16913c3ef65c 100644 --- a/drivers/soc/loongson/loongson2_guts.c +++ b/drivers/soc/loongson/loongson2_guts.c @@ -114,8 +114,11 @@ static int loongson2_guts_probe(struct platform_device *pdev) if (of_property_read_string(root, "model", &machine)) of_property_read_string_index(root, "compatible", 0, &machine); of_node_put(root); - if (machine) + if (machine) { soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL); + if (!soc_dev_attr.machine) + return -ENOMEM; + } svr = loongson2_guts_get_svr(); soc_die = loongson2_soc_die_match(svr, loongson2_soc_die); diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index f7a35b3656bb..c468926561b4 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -14,22 +14,21 @@ #define MT8167_DSI0_SEL_IN_RDMA0 0x1 static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0, - MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0 - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0, - MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0 - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0, - MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0 - }, + MMSYS_ROUTE(OVL0, COLOR0, + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, + OVL0_MOUT_EN_COLOR0), + MMSYS_ROUTE(DITHER0, RDMA0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0, + MT8167_DITHER_MOUT_EN_RDMA0), + MMSYS_ROUTE(OVL0, COLOR0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, + COLOR0_SEL_IN_OVL0), + MMSYS_ROUTE(RDMA0, DSI0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0, + MT8167_DSI0_SEL_IN_RDMA0), + MMSYS_ROUTE(RDMA0, DSI0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0, + MT8167_RDMA0_SOUT_DSI0), }; #endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8173-mmsys.h b/drivers/soc/mediatek/mt8173-mmsys.h index 9d24e381271e..957876d7c166 100644 --- a/drivers/soc/mediatek/mt8173-mmsys.h +++ b/drivers/soc/mediatek/mt8173-mmsys.h @@ -33,63 +33,48 @@ #define MT8173_RDMA0_SOUT_COLOR0 BIT(0) static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, - MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0 - }, { - DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, - MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, - MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0 - }, { - DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, - MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, - MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0 - }, { - DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0, - MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, - MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */ - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, - MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, - MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */ - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, - MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0 - }, { - DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0, - MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, - MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */ - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, - MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, - MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */ - }, { - DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, - MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, - MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */ - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, - MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, - MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1 - }, { - DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, - MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, - MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1 - }, { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, - RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, - MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, - COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1 - }, { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8173_DISP_REG_CONFIG_DPI_SEL_IN, - MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1 - } + MMSYS_ROUTE(OVL0, COLOR0, + MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0, + MT8173_OVL0_MOUT_EN_COLOR0), + MMSYS_ROUTE(OD0, RDMA0, + MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0, + MT8173_OD0_MOUT_EN_RDMA0), + MMSYS_ROUTE(UFOE, DSI0, + MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0, + MT8173_UFOE_MOUT_EN_DSI0), + MMSYS_ROUTE(COLOR0, AAL0, + MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE, + 0 /* SOUT to AAL */), + MMSYS_ROUTE(RDMA0, UFOE, + MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0, + 0 /* SOUT to UFOE */), + MMSYS_ROUTE(OVL0, COLOR0, + MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0, + MT8173_COLOR0_SEL_IN_OVL0), + MMSYS_ROUTE(AAL0, COLOR0, + MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE, + 0 /* SEL_IN from COLOR0 */), + MMSYS_ROUTE(RDMA0, UFOE, + MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0, + 0 /* SEL_IN from RDMA0 */), + MMSYS_ROUTE(UFOE, DSI0, + MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE, + 0 /* SEL_IN from UFOE */), + MMSYS_ROUTE(OVL1, COLOR1, + MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1, + MT8173_OVL1_MOUT_EN_COLOR1), + MMSYS_ROUTE(GAMMA, RDMA1, + MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1, + MT8173_GAMMA_MOUT_EN_RDMA1), + MMSYS_ROUTE(RDMA1, DPI0, + MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DPI0), + MMSYS_ROUTE(OVL1, COLOR1, + MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1, + COLOR1_SEL_IN_OVL1), + MMSYS_ROUTE(RDMA1, DPI0, + MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK, + MT8173_DPI0_SEL_IN_RDMA1), }; #endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index ff6be1703469..123384958c4b 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -28,35 +28,27 @@ #define MT8183_MMSYS_SW0_RST_B 0x140 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, - MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L, - MT8183_OVL0_MOUT_EN_OVL0_2L - }, { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0, - MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 - }, { - DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, - MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1, - MT8183_OVL1_2L_MOUT_EN_RDMA1 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0, - MT8183_DITHER0_MOUT_IN_DSI0 - }, { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L, - MT8183_DISP_PATH0_SEL_IN_OVL0_2L - }, { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1, - MT8183_DPI0_SEL_IN_RDMA1 - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0, - MT8183_RDMA0_SOUT_COLOR0 - } + MMSYS_ROUTE(OVL0, OVL_2L0, + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L, + MT8183_OVL0_MOUT_EN_OVL0_2L), + MMSYS_ROUTE(OVL_2L0, RDMA0, + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0, + MT8183_OVL0_2L_MOUT_EN_DISP_PATH0), + MMSYS_ROUTE(OVL_2L1, RDMA1, + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1, + MT8183_OVL1_2L_MOUT_EN_RDMA1), + MMSYS_ROUTE(DITHER0, DSI0, + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0, + MT8183_DITHER0_MOUT_IN_DSI0), + MMSYS_ROUTE(OVL_2L0, RDMA0, + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L, + MT8183_DISP_PATH0_SEL_IN_OVL0_2L), + MMSYS_ROUTE(RDMA1, DPI0, + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1, + MT8183_DPI0_SEL_IN_RDMA1), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0, + MT8183_RDMA0_SOUT_COLOR0), }; #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h index 279d4138525b..354664be72bd 100644 --- a/drivers/soc/mediatek/mt8186-mmsys.h +++ b/drivers/soc/mediatek/mt8186-mmsys.h @@ -63,61 +63,39 @@ #define MT8186_MMSYS_SW0_RST_B 0x160 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, - MT8186_OVL0_MOUT_TO_RDMA0 - }, - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, - MT8186_RDMA0_FROM_OVL0 - }, - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, - MT8186_OVL0_GO_BLEND - }, - { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, - MT8186_RDMA0_SOUT_TO_COLOR0 - }, - { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, - MT8186_DITHER0_MOUT_TO_DSI0, - }, - { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, - MT8186_DSI0_FROM_DITHER0 - }, - { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, - MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, - MT8186_OVL0_2L_MOUT_TO_RDMA1 - }, - { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, - MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, - MT8186_RDMA1_FROM_OVL0_2L - }, - { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, - MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, - MT8186_OVL0_2L_GO_BLEND - }, - { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, - MT8186_RDMA1_MOUT_TO_DPI0_SEL - }, - { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, - MT8186_DPI0_FROM_RDMA1 - }, + MMSYS_ROUTE(OVL0, RDMA0, + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, + MT8186_OVL0_MOUT_TO_RDMA0), + MMSYS_ROUTE(OVL0, RDMA0, + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, + MT8186_RDMA0_FROM_OVL0), + MMSYS_ROUTE(OVL0, RDMA0, + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, + MT8186_OVL0_GO_BLEND), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, + MT8186_RDMA0_SOUT_TO_COLOR0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, + MT8186_DITHER0_MOUT_TO_DSI0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, + MT8186_DSI0_FROM_DITHER0), + MMSYS_ROUTE(OVL_2L0, RDMA1, + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, + MT8186_OVL0_2L_MOUT_TO_RDMA1), + MMSYS_ROUTE(OVL_2L0, RDMA1, + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, + MT8186_RDMA1_FROM_OVL0_2L), + MMSYS_ROUTE(OVL_2L0, RDMA1, + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, + MT8186_OVL0_2L_GO_BLEND), + MMSYS_ROUTE(RDMA1, DPI0, + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, + MT8186_RDMA1_MOUT_TO_DPI0_SEL), + MMSYS_ROUTE(RDMA1, DPI0, + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, + MT8186_DPI0_FROM_RDMA1), }; #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 6bebf1a69fc0..99080afead7e 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -202,158 +202,126 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = { }; static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, - MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, - MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, - MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, - MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, - MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8188_VDO0_DSC_WARP_SEL, - MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, - MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, - MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, - MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, - MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, - MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DISP_DITHER0_SEL_OUT, - MT8188_SOUT_DISP_DITHER0_TO_MASK, - MT8188_SOUT_DISP_DITHER0_TO_DSI0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_DISP_DITHER0_SEL_OUT, - MT8188_SOUT_DISP_DITHER0_TO_MASK, - MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE - }, + MMSYS_ROUTE(OVL0, RDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0), + MMSYS_ROUTE(OVL0, WDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0), + MMSYS_ROUTE(OVL0, RDMA0, + MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, + MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, + MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, DP_INTF0, + MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE), + MMSYS_ROUTE(DSC0, DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0), + MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN), + MMSYS_ROUTE(DITHER0, DSI0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DSI0), + MMSYS_ROUTE(DITHER0, MERGE0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0), + MMSYS_ROUTE(DITHER0, DP_INTF0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DPI0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(MERGE0, WDMA0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0), + MMSYS_ROUTE(MERGE0, DSC0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN), + MMSYS_ROUTE(DSC0, DSI0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE), }; static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { - { - DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, - MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 - }, { - DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, - MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 - }, { - DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, - MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN1_SEL - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN2_SEL - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN3_SEL - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN4_SEL - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), - MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), - MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), - MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), - MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), - MT8188_MERGE4_SOUT_TO_DPI1_SEL - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), - MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), - MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL - } + MMSYS_ROUTE(MDP_RDMA0, MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0), + MMSYS_ROUTE(MDP_RDMA1, MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1), + MMSYS_ROUTE(MDP_RDMA2, MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL), }; #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h index a016d80b4bc1..7cafa2455fd0 100644 --- a/drivers/soc/mediatek/mt8192-mmsys.h +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -31,47 +31,36 @@ #define MT8192_DSI0_SEL_IN_DITHER0 0x1 static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { - { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, - MT8192_OVL0_MOUT_EN_DISP_RDMA0 - }, { - DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, - MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, - MT8192_OVL2_2L_MOUT_EN_RDMA4 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, - MT8192_DITHER0_MOUT_IN_DSI0 - }, { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, - MT8192_RDMA0_SEL_IN_OVL0_2L - }, { - DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, - MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, - MT8192_AAL0_SEL_IN_CCORR0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, - MT8192_DSI0_SEL_IN_DITHER0 - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, - MT8192_RDMA0_SOUT_COLOR0 - }, { - DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, - MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, - MT8192_CCORR0_SOUT_AAL0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, - MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, - MT8192_DISP_OVL0_GO_BG - }, { - DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, - MT8192_DISP_OVL0_2L_GO_BLEND - } + MMSYS_ROUTE(OVL_2L0, RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + MT8192_OVL0_MOUT_EN_DISP_RDMA0), + MMSYS_ROUTE(OVL_2L2, RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, + MT8192_OVL2_2L_MOUT_EN_RDMA4), + MMSYS_ROUTE(DITHER0, DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, + MT8192_DITHER0_MOUT_IN_DSI0), + MMSYS_ROUTE(OVL_2L0, RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, + MT8192_RDMA0_SEL_IN_OVL0_2L), + MMSYS_ROUTE(CCORR, AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, + MT8192_AAL0_SEL_IN_CCORR0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, + MT8192_DSI0_SEL_IN_DITHER0), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, + MT8192_RDMA0_SOUT_COLOR0), + MMSYS_ROUTE(CCORR, AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, + MT8192_CCORR0_SOUT_AAL0), + MMSYS_ROUTE(OVL0, OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + MT8192_DISP_OVL0_GO_BG), + MMSYS_ROUTE(OVL_2L0, RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + MT8192_DISP_OVL0_2L_GO_BLEND), }; #endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 9be2df2832a4..f69929a2a4d4 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -160,370 +160,278 @@ #define MT8195_SVPP3_MDP_RSZ BIT(5) static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, - MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, - MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, - MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, - MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, - MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, - MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, - MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, - MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, - MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, - MT8195_SEL_IN_DSI1_FROM_VPP_MERGE - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, - MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, - MT8195_SOUT_DISP_DITHER0_TO_DSI0 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, - MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, - MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSI1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE - } + MMSYS_ROUTE(OVL0, RDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0), + MMSYS_ROUTE(OVL0, WDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0), + MMSYS_ROUTE(OVL0, OVL1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1), + MMSYS_ROUTE(OVL1, RDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1), + MMSYS_ROUTE(OVL1, WDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1), + MMSYS_ROUTE(OVL1, OVL0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DITHER1, MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1), + MMSYS_ROUTE(MERGE5, MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0), + MMSYS_ROUTE(MERGE0, DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE), + MMSYS_ROUTE(DITHER1, DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1), + MMSYS_ROUTE(MERGE0, DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE), + MMSYS_ROUTE(MERGE0, DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), + MMSYS_ROUTE(MERGE0, DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), + MMSYS_ROUTE(MERGE0, DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), + MMSYS_ROUTE(DSC1, DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), + MMSYS_ROUTE(DSC1, DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), + MMSYS_ROUTE(DSC1, DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), + MMSYS_ROUTE(DSC0, DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DSC0, DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DSC0, DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DSC1, DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE), + MMSYS_ROUTE(MERGE5, DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0), + MMSYS_ROUTE(DSC0, DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DITHER0, DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DSC1, DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT), + MMSYS_ROUTE(MERGE0, DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE), + MMSYS_ROUTE(OVL1, WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1), + MMSYS_ROUTE(MERGE0, WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE), + MMSYS_ROUTE(DSC1, DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC1, DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC1, DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC1, DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC1, DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC1, MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), + MMSYS_ROUTE(DITHER1, DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), + MMSYS_ROUTE(DITHER1, DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), + MMSYS_ROUTE(DITHER1, DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), + MMSYS_ROUTE(DITHER1, DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), + MMSYS_ROUTE(OVL0, WDMA0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN), + MMSYS_ROUTE(DITHER0, DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSI0), + MMSYS_ROUTE(DITHER1, DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN), + MMSYS_ROUTE(DITHER1, MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE), + MMSYS_ROUTE(DITHER1, DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), + MMSYS_ROUTE(DITHER1, DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), + MMSYS_ROUTE(DITHER1, DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), + MMSYS_ROUTE(DITHER1, DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), + MMSYS_ROUTE(DITHER1, DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), + MMSYS_ROUTE(MERGE5, MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE), + MMSYS_ROUTE(MERGE5, DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSI1), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(MERGE0, DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(MERGE0, DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(MERGE0, WDMA1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1), + MMSYS_ROUTE(MERGE0, DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN), + MMSYS_ROUTE(MERGE0, DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN), + MMSYS_ROUTE(DSC0, DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0), + MMSYS_ROUTE(DSC0, DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), + MMSYS_ROUTE(DSC0, DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), + MMSYS_ROUTE(DSC0, DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE), + MMSYS_ROUTE(DSC1, DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1), + MMSYS_ROUTE(DSC1, DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0), + MMSYS_ROUTE(DSC1, DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(DSC1, DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(DSC1, DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(DSC1, MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE), }; static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { - { - DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, - MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), - MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 - }, { - DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, - MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), - MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 - }, { - DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, - MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), - MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8195_SOUT_TO_MIXER_IN1_SEL - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8195_SOUT_TO_MIXER_IN2_SEL - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8195_SOUT_TO_MIXER_IN3_SEL - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8195_SOUT_TO_MIXER_IN4_SEL - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), - MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), - MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), - MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), - MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), - MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), - MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), - MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), - MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), - MT8195_MERGE4_SOUT_TO_DPI1_SEL - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), - MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), - MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL - } + MMSYS_ROUTE(MDP_RDMA0, MERGE1, + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0), + MMSYS_ROUTE(MDP_RDMA1, MERGE1, + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1), + MMSYS_ROUTE(MDP_RDMA2, MERGE2, + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN1_SEL), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN2_SEL), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN3_SEL), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN4_SEL), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DPI1_SEL), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL), }; #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h index 7abaf048d91e..533a3fd0923b 100644 --- a/drivers/soc/mediatek/mt8365-mmsys.h +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -14,8 +14,9 @@ #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8 #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc +#define MT8365_DISP_MS_IN_OUT_MASK GENMASK(3, 0) #define MT8365_RDMA0_SOUT_COLOR0 0x1 -#define MT8365_DITHER_MOUT_EN_DSI0 0x1 +#define MT8365_DITHER_MOUT_EN_DSI0 BIT(0) #define MT8365_DSI0_SEL_IN_DITHER 0x1 #define MT8365_RDMA0_SEL_IN_OVL0 0x0 #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 @@ -27,56 +28,37 @@ #define MT8365_DPI0_SEL_IN_RDMA1 0x0 static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, - MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL - }, - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, - MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0 - }, - { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, - MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0 - }, - { - DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR, - MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, - MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 - }, - { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, - MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 - }, - { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, - MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER - }, - { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, - MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 - }, - { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00, - MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK - }, - { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, - MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1 - }, - { - DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL, - MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0 - }, + MMSYS_ROUTE(OVL0, RDMA0, + MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL), + MMSYS_ROUTE(OVL0, RDMA0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0), + MMSYS_ROUTE(COLOR0, CCORR, + MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0), + MMSYS_ROUTE(RDMA1, DPI0, + MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00, + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK), + MMSYS_ROUTE(RDMA1, DPI0, + MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1), + MMSYS_ROUTE(RDMA1, DPI0, + MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL, + MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0), }; #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c index 83bf46fdcf2d..41add5636b03 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -446,6 +446,46 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev) return 0; } +static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_v1 = { 0, 0, 0 }; +static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_v2 = { + .max_dram_nom_bw = 255, + .max_dram_peak_bw = 255, + .max_dram_hrt_bw = 1023, +}; + +static const struct dvfsrc_opp dvfsrc_opp_mt6893_lp4[] = { + { 0, 0 }, { 1, 0 }, { 2, 0 }, { 3, 0 }, + { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, + { 0, 2 }, { 1, 2 }, { 2, 2 }, { 3, 2 }, + { 0, 3 }, { 1, 3 }, { 2, 3 }, { 3, 3 }, + { 1, 4 }, { 2, 4 }, { 3, 4 }, { 2, 5 }, + { 3, 5 }, { 3, 6 }, { 4, 6 }, { 4, 7 }, +}; + +static const struct dvfsrc_opp_desc dvfsrc_opp_mt6893_desc[] = { + [0] = { + .opps = dvfsrc_opp_mt6893_lp4, + .num_opp = ARRAY_SIZE(dvfsrc_opp_mt6893_lp4), + } +}; + +static const struct dvfsrc_soc_data mt6893_data = { + .opps_desc = dvfsrc_opp_mt6893_desc, + .regs = dvfsrc_mt8195_regs, + .get_target_level = dvfsrc_get_target_level_v2, + .get_current_level = dvfsrc_get_current_level_v2, + .get_vcore_level = dvfsrc_get_vcore_level_v2, + .get_vscp_level = dvfsrc_get_vscp_level_v2, + .set_dram_bw = dvfsrc_set_dram_bw_v1, + .set_dram_peak_bw = dvfsrc_set_dram_peak_bw_v1, + .set_dram_hrt_bw = dvfsrc_set_dram_hrt_bw_v1, + .set_vcore_level = dvfsrc_set_vcore_level_v2, + .set_vscp_level = dvfsrc_set_vscp_level_v2, + .wait_for_opp_level = dvfsrc_wait_for_opp_level_v2, + .wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v1, + .bw_constraints = &dvfsrc_bw_constr_v2, +}; + static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = { { 0, 0 }, { 0, 1 }, { 0, 2 }, { 1, 2 }, }; @@ -469,8 +509,6 @@ static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = { } }; -static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_mt8183 = { 0, 0, 0 }; - static const struct dvfsrc_soc_data mt8183_data = { .opps_desc = dvfsrc_opp_mt8183_desc, .regs = dvfsrc_mt8183_regs, @@ -482,7 +520,7 @@ static const struct dvfsrc_soc_data mt8183_data = { .set_vcore_level = dvfsrc_set_vcore_level_v1, .wait_for_opp_level = dvfsrc_wait_for_opp_level_v1, .wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v1, - .bw_constraints = &dvfsrc_bw_constr_mt8183, + .bw_constraints = &dvfsrc_bw_constr_v1, }; static const struct dvfsrc_opp dvfsrc_opp_mt8195_lp4[] = { @@ -501,12 +539,6 @@ static const struct dvfsrc_opp_desc dvfsrc_opp_mt8195_desc[] = { } }; -static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_mt8195 = { - .max_dram_nom_bw = 255, - .max_dram_peak_bw = 255, - .max_dram_hrt_bw = 1023, -}; - static const struct dvfsrc_soc_data mt8195_data = { .opps_desc = dvfsrc_opp_mt8195_desc, .regs = dvfsrc_mt8195_regs, @@ -521,10 +553,11 @@ static const struct dvfsrc_soc_data mt8195_data = { .set_vscp_level = dvfsrc_set_vscp_level_v2, .wait_for_opp_level = dvfsrc_wait_for_opp_level_v2, .wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v1, - .bw_constraints = &dvfsrc_bw_constr_mt8195, + .bw_constraints = &dvfsrc_bw_constr_v2, }; static const struct of_device_id mtk_dvfsrc_of_match[] = { + { .compatible = "mediatek,mt6893-dvfsrc", .data = &mt6893_data }, { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_data }, { .compatible = "mediatek,mt8195-dvfsrc", .data = &mt8195_data }, { /* sentinel */ } diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index d370192737ca..fe628d5f5198 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -80,6 +80,20 @@ #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) +/* + * This macro adds a compile time check to make sure that the in/out + * selection bit(s) fit in the register mask, similar to bitfield + * macros, but this does not transform the value. + */ +#define MMSYS_ROUTE(from, to, reg_addr, reg_mask, selection) \ + { DDP_COMPONENT_##from, DDP_COMPONENT_##to, reg_addr, reg_mask, \ + (__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") + \ + __BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \ + #selection " does not fit in " \ + #reg_mask) + \ + (selection)) \ + } + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 5250c1d702eb..aaa965d4b050 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -155,6 +155,7 @@ #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DPI1 38 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 #define MT8195_MUTEX_MOD_DISP_OVL0 0 @@ -289,6 +290,7 @@ #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 #define MT8188_MUTEX_SOF_DP_INTF1 4 +#define MT8188_MUTEX_SOF_DPI1 5 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -301,6 +303,7 @@ #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) +#define MT8188_MUTEX_EOF_DPI1 (MT8188_MUTEX_SOF_DPI1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -472,6 +475,7 @@ static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, + [DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1, [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, @@ -686,6 +690,8 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, + [MUTEX_SOF_DPI1] = + MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1, [MUTEX_SOF_DP_INTF0] = MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, [MUTEX_SOF_DP_INTF1] = diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-socinfo.c index 123b12cd2543..c697a0398d91 100644 --- a/drivers/soc/mediatek/mtk-socinfo.c +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -56,29 +56,39 @@ static struct socinfo_data socinfo_data_table[] = { MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EHZA", "Kompanio 1200", 0x81950304, CELL_NOT_USED), MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EZA", "Kompanio 1380", 0x81950400, CELL_NOT_USED), MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EHZA", "Kompanio 1380", 0x81950404, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8370", "MT8370AV/AZA", "Genio 510", 0x83700000, 0x00000081), + MTK_SOCINFO_ENTRY("MT8390", "MT8390AV/AZA", "Genio 700", 0x83900000, 0x00000080), MTK_SOCINFO_ENTRY("MT8395", "MT8395AV/ZA", "Genio 1200", 0x83950100, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8395", "MT8395AV/ZA", "Genio 1200", 0x83950800, CELL_NOT_USED), }; static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfop) { struct soc_device_attribute *attrs; - static char machine[30] = {0}; + struct socinfo_data *data = mtk_socinfop->socinfo_data; static const char *soc_manufacturer = "MediaTek"; attrs = devm_kzalloc(mtk_socinfop->dev, sizeof(*attrs), GFP_KERNEL); if (!attrs) return -ENOMEM; - snprintf(machine, sizeof(machine), "%s (%s)", mtk_socinfop->socinfo_data->marketing_name, - mtk_socinfop->socinfo_data->soc_name); - attrs->family = soc_manufacturer; - attrs->machine = machine; + if (data->marketing_name != NULL && data->marketing_name[0] != '\0') + attrs->family = devm_kasprintf(mtk_socinfop->dev, GFP_KERNEL, "MediaTek %s", + data->marketing_name); + else + attrs->family = soc_manufacturer; + + attrs->soc_id = data->soc_name; + /* + * The "machine" field will be populated automatically with the model + * name from board DTS (if available). + **/ mtk_socinfop->soc_dev = soc_device_register(attrs); if (IS_ERR(mtk_socinfop->soc_dev)) return PTR_ERR(mtk_socinfop->soc_dev); - dev_info(mtk_socinfop->dev, "%s %s SoC detected.\n", soc_manufacturer, attrs->machine); + dev_info(mtk_socinfop->dev, "%s (%s) SoC detected.\n", attrs->family, attrs->soc_id); return 0; } diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 393d2d1d275f..c467b55b4174 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -11,6 +11,7 @@ #include <linux/cleanup.h> #include <linux/clk.h> #include <linux/delay.h> +#include <linux/device.h> #include <linux/iopoll.h> #include <linux/of.h> #include <linux/of_platform.h> @@ -20,20 +21,63 @@ #include <soc/qcom/ice.h> -#define AES_256_XTS_KEY_SIZE 64 +#define AES_256_XTS_KEY_SIZE 64 /* for raw keys only */ +#define QCOM_ICE_HWKM_WRAPPED_KEY_SIZE 100 /* assuming HWKM v2 */ /* QCOM ICE registers */ + +#define QCOM_ICE_REG_CONTROL 0x0000 +#define QCOM_ICE_LEGACY_MODE_ENABLED BIT(0) + #define QCOM_ICE_REG_VERSION 0x0008 + #define QCOM_ICE_REG_FUSE_SETTING 0x0010 +#define QCOM_ICE_FUSE_SETTING_MASK BIT(0) +#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK BIT(1) +#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK BIT(2) + #define QCOM_ICE_REG_BIST_STATUS 0x0070 +#define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28) + #define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 -/* BIST ("built-in self-test") status flags */ -#define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28) +#define QCOM_ICE_REG_CRYPTOCFG_BASE 0x4040 +#define QCOM_ICE_REG_CRYPTOCFG_SIZE 0x80 +#define QCOM_ICE_REG_CRYPTOCFG(slot) (QCOM_ICE_REG_CRYPTOCFG_BASE + \ + QCOM_ICE_REG_CRYPTOCFG_SIZE * (slot)) +union crypto_cfg { + __le32 regval; + struct { + u8 dusize; + u8 capidx; + u8 reserved; +#define QCOM_ICE_HWKM_CFG_ENABLE_VAL BIT(7) + u8 cfge; + }; +}; + +/* QCOM ICE HWKM (Hardware Key Manager) registers */ -#define QCOM_ICE_FUSE_SETTING_MASK 0x1 -#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 -#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 +#define HWKM_OFFSET 0x8000 + +#define QCOM_ICE_REG_HWKM_TZ_KM_CTL (HWKM_OFFSET + 0x1000) +#define QCOM_ICE_HWKM_DISABLE_CRC_CHECKS_VAL (BIT(1) | BIT(2)) + +#define QCOM_ICE_REG_HWKM_TZ_KM_STATUS (HWKM_OFFSET + 0x1004) +#define QCOM_ICE_HWKM_KT_CLEAR_DONE BIT(0) +#define QCOM_ICE_HWKM_BOOT_CMD_LIST0_DONE BIT(1) +#define QCOM_ICE_HWKM_BOOT_CMD_LIST1_DONE BIT(2) +#define QCOM_ICE_HWKM_CRYPTO_BIST_DONE_V2 BIT(7) +#define QCOM_ICE_HWKM_BIST_DONE_V2 BIT(9) + +#define QCOM_ICE_REG_HWKM_BANK0_BANKN_IRQ_STATUS (HWKM_OFFSET + 0x2008) +#define QCOM_ICE_HWKM_RSP_FIFO_CLEAR_VAL BIT(3) + +#define QCOM_ICE_REG_HWKM_BANK0_BBAC_0 (HWKM_OFFSET + 0x5000) +#define QCOM_ICE_REG_HWKM_BANK0_BBAC_1 (HWKM_OFFSET + 0x5004) +#define QCOM_ICE_REG_HWKM_BANK0_BBAC_2 (HWKM_OFFSET + 0x5008) +#define QCOM_ICE_REG_HWKM_BANK0_BBAC_3 (HWKM_OFFSET + 0x500C) +#define QCOM_ICE_REG_HWKM_BANK0_BBAC_4 (HWKM_OFFSET + 0x5010) #define qcom_ice_writel(engine, val, reg) \ writel((val), (engine)->base + (reg)) @@ -41,11 +85,18 @@ #define qcom_ice_readl(engine, reg) \ readl((engine)->base + (reg)) +static bool qcom_ice_use_wrapped_keys; +module_param_named(use_wrapped_keys, qcom_ice_use_wrapped_keys, bool, 0660); +MODULE_PARM_DESC(use_wrapped_keys, + "Support wrapped keys instead of raw keys, if available on the platform"); + struct qcom_ice { struct device *dev; void __iomem *base; struct clk *core_clk; + bool use_hwkm; + bool hwkm_init_complete; }; static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -75,6 +126,35 @@ static bool qcom_ice_check_supported(struct qcom_ice *ice) return false; } + /* + * Check for HWKM support and decide whether to use it or not. ICE + * v3.2.1 and later have HWKM v2. ICE v3.2.0 has HWKM v1. Earlier ICE + * versions don't have HWKM at all. However, for HWKM to be fully + * usable by Linux, the TrustZone software also needs to support certain + * SCM calls including the ones to generate and prepare keys. That + * effectively makes the earliest supported SoC be SM8650, which has + * HWKM v2. Therefore, this driver doesn't include support for HWKM v1, + * and it checks for the SCM call support before it decides to use HWKM. + * + * Also, since HWKM and legacy mode are mutually exclusive, and + * ICE-capable storage driver(s) need to know early on whether to + * advertise support for raw keys or wrapped keys, HWKM cannot be used + * unconditionally. A module parameter is used to opt into using it. + */ + if ((major >= 4 || + (major == 3 && (minor >= 3 || (minor == 2 && step >= 1)))) && + qcom_scm_has_wrapped_key_support()) { + if (qcom_ice_use_wrapped_keys) { + dev_info(dev, "Using HWKM. Supporting wrapped keys only.\n"); + ice->use_hwkm = true; + } else { + dev_info(dev, "Not using HWKM. Supporting raw keys only.\n"); + } + } else if (qcom_ice_use_wrapped_keys) { + dev_warn(dev, "A supported HWKM is not present. Ignoring qcom_ice.use_wrapped_keys=1.\n"); + } else { + dev_info(dev, "A supported HWKM is not present. Supporting raw keys only.\n"); + } return true; } @@ -122,17 +202,71 @@ static int qcom_ice_wait_bist_status(struct qcom_ice *ice) err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, regval, !(regval & QCOM_ICE_BIST_STATUS_MASK), 50, 5000); - if (err) + if (err) { dev_err(ice->dev, "Timed out waiting for ICE self-test to complete\n"); + return err; + } - return err; + if (ice->use_hwkm && + qcom_ice_readl(ice, QCOM_ICE_REG_HWKM_TZ_KM_STATUS) != + (QCOM_ICE_HWKM_KT_CLEAR_DONE | + QCOM_ICE_HWKM_BOOT_CMD_LIST0_DONE | + QCOM_ICE_HWKM_BOOT_CMD_LIST1_DONE | + QCOM_ICE_HWKM_CRYPTO_BIST_DONE_V2 | + QCOM_ICE_HWKM_BIST_DONE_V2)) { + dev_err(ice->dev, "HWKM self-test error!\n"); + /* + * Too late to revoke use_hwkm here, as it was already + * propagated up the stack into the crypto capabilities. + */ + } + return 0; +} + +static void qcom_ice_hwkm_init(struct qcom_ice *ice) +{ + u32 regval; + + if (!ice->use_hwkm) + return; + + BUILD_BUG_ON(QCOM_ICE_HWKM_WRAPPED_KEY_SIZE > + BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE); + /* + * When ICE is in HWKM mode, it only supports wrapped keys. + * When ICE is in legacy mode, it only supports raw keys. + * + * Put ICE in HWKM mode. ICE defaults to legacy mode. + */ + regval = qcom_ice_readl(ice, QCOM_ICE_REG_CONTROL); + regval &= ~QCOM_ICE_LEGACY_MODE_ENABLED; + qcom_ice_writel(ice, regval, QCOM_ICE_REG_CONTROL); + + /* Disable CRC checks. This HWKM feature is not used. */ + qcom_ice_writel(ice, QCOM_ICE_HWKM_DISABLE_CRC_CHECKS_VAL, + QCOM_ICE_REG_HWKM_TZ_KM_CTL); + + /* + * Allow the HWKM slave to read and write the keyslots in the ICE HWKM + * slave. Without this, TrustZone cannot program keys into ICE. + */ + qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_0); + qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_1); + qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_2); + qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_3); + qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_4); + + /* Clear the HWKM response FIFO. */ + qcom_ice_writel(ice, QCOM_ICE_HWKM_RSP_FIFO_CLEAR_VAL, + QCOM_ICE_REG_HWKM_BANK0_BANKN_IRQ_STATUS); + ice->hwkm_init_complete = true; } int qcom_ice_enable(struct qcom_ice *ice) { qcom_ice_low_power_mode_enable(ice); qcom_ice_optimization_enable(ice); - + qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } EXPORT_SYMBOL_GPL(qcom_ice_enable); @@ -148,7 +282,7 @@ int qcom_ice_resume(struct qcom_ice *ice) err); return err; } - + qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } EXPORT_SYMBOL_GPL(qcom_ice_resume); @@ -156,15 +290,58 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { clk_disable_unprepare(ice->core_clk); + ice->hwkm_init_complete = false; return 0; } EXPORT_SYMBOL_GPL(qcom_ice_suspend); -int qcom_ice_program_key(struct qcom_ice *ice, - u8 algorithm_id, u8 key_size, - const u8 crypto_key[], u8 data_unit_size, - int slot) +static unsigned int translate_hwkm_slot(struct qcom_ice *ice, unsigned int slot) +{ + return slot * 2; +} + +static int qcom_ice_program_wrapped_key(struct qcom_ice *ice, unsigned int slot, + const struct blk_crypto_key *bkey) +{ + struct device *dev = ice->dev; + union crypto_cfg cfg = { + .dusize = bkey->crypto_cfg.data_unit_size / 512, + .capidx = QCOM_SCM_ICE_CIPHER_AES_256_XTS, + .cfge = QCOM_ICE_HWKM_CFG_ENABLE_VAL, + }; + int err; + + if (!ice->use_hwkm) { + dev_err_ratelimited(dev, "Got wrapped key when not using HWKM\n"); + return -EINVAL; + } + if (!ice->hwkm_init_complete) { + dev_err_ratelimited(dev, "HWKM not yet initialized\n"); + return -EINVAL; + } + + /* Clear CFGE before programming the key. */ + qcom_ice_writel(ice, 0x0, QCOM_ICE_REG_CRYPTOCFG(slot)); + + /* Call into TrustZone to program the wrapped key using HWKM. */ + err = qcom_scm_ice_set_key(translate_hwkm_slot(ice, slot), bkey->bytes, + bkey->size, cfg.capidx, cfg.dusize); + if (err) { + dev_err_ratelimited(dev, + "qcom_scm_ice_set_key failed; err=%d, slot=%u\n", + err, slot); + return err; + } + + /* Set CFGE after programming the key. */ + qcom_ice_writel(ice, le32_to_cpu(cfg.regval), + QCOM_ICE_REG_CRYPTOCFG(slot)); + return 0; +} + +int qcom_ice_program_key(struct qcom_ice *ice, unsigned int slot, + const struct blk_crypto_key *blk_key) { struct device *dev = ice->dev; union { @@ -175,15 +352,26 @@ int qcom_ice_program_key(struct qcom_ice *ice, int err; /* Only AES-256-XTS has been tested so far. */ - if (algorithm_id != QCOM_ICE_CRYPTO_ALG_AES_XTS || - key_size != QCOM_ICE_CRYPTO_KEY_SIZE_256) { - dev_err_ratelimited(dev, - "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", - algorithm_id, key_size); + if (blk_key->crypto_cfg.crypto_mode != + BLK_ENCRYPTION_MODE_AES_256_XTS) { + dev_err_ratelimited(dev, "Unsupported crypto mode: %d\n", + blk_key->crypto_cfg.crypto_mode); + return -EINVAL; + } + + if (blk_key->crypto_cfg.key_type == BLK_CRYPTO_KEY_TYPE_HW_WRAPPED) + return qcom_ice_program_wrapped_key(ice, slot, blk_key); + + if (ice->use_hwkm) { + dev_err_ratelimited(dev, "Got raw key when using HWKM\n"); return -EINVAL; } - memcpy(key.bytes, crypto_key, AES_256_XTS_KEY_SIZE); + if (blk_key->size != AES_256_XTS_KEY_SIZE) { + dev_err_ratelimited(dev, "Incorrect key size\n"); + return -EINVAL; + } + memcpy(key.bytes, blk_key->bytes, AES_256_XTS_KEY_SIZE); /* The SCM call requires that the key words are encoded in big endian */ for (i = 0; i < ARRAY_SIZE(key.words); i++) @@ -191,7 +379,7 @@ int qcom_ice_program_key(struct qcom_ice *ice, err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, QCOM_SCM_ICE_CIPHER_AES_256_XTS, - data_unit_size); + blk_key->crypto_cfg.data_unit_size / 512); memzero_explicit(&key, sizeof(key)); @@ -201,10 +389,131 @@ EXPORT_SYMBOL_GPL(qcom_ice_program_key); int qcom_ice_evict_key(struct qcom_ice *ice, int slot) { + if (ice->hwkm_init_complete) + slot = translate_hwkm_slot(ice, slot); return qcom_scm_ice_invalidate_key(slot); } EXPORT_SYMBOL_GPL(qcom_ice_evict_key); +/** + * qcom_ice_get_supported_key_type() - Get the supported key type + * @ice: ICE driver data + * + * Return: the blk-crypto key type that the ICE driver is configured to use. + * This is the key type that ICE-capable storage drivers should advertise as + * supported in the crypto capabilities of any disks they register. + */ +enum blk_crypto_key_type qcom_ice_get_supported_key_type(struct qcom_ice *ice) +{ + if (ice->use_hwkm) + return BLK_CRYPTO_KEY_TYPE_HW_WRAPPED; + return BLK_CRYPTO_KEY_TYPE_RAW; +} +EXPORT_SYMBOL_GPL(qcom_ice_get_supported_key_type); + +/** + * qcom_ice_derive_sw_secret() - Derive software secret from wrapped key + * @ice: ICE driver data + * @eph_key: an ephemerally-wrapped key + * @eph_key_size: size of @eph_key in bytes + * @sw_secret: output buffer for the software secret + * + * Use HWKM to derive the "software secret" from a hardware-wrapped key that is + * given in ephemerally-wrapped form. + * + * Return: 0 on success; -EBADMSG if the given ephemerally-wrapped key is + * invalid; or another -errno value. + */ +int qcom_ice_derive_sw_secret(struct qcom_ice *ice, + const u8 *eph_key, size_t eph_key_size, + u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) +{ + int err = qcom_scm_derive_sw_secret(eph_key, eph_key_size, + sw_secret, + BLK_CRYPTO_SW_SECRET_SIZE); + if (err == -EIO || err == -EINVAL) + err = -EBADMSG; /* probably invalid key */ + return err; +} +EXPORT_SYMBOL_GPL(qcom_ice_derive_sw_secret); + +/** + * qcom_ice_generate_key() - Generate a wrapped key for inline encryption + * @ice: ICE driver data + * @lt_key: output buffer for the long-term wrapped key + * + * Use HWKM to generate a new key and return it as a long-term wrapped key. + * + * Return: the size of the resulting wrapped key on success; -errno on failure. + */ +int qcom_ice_generate_key(struct qcom_ice *ice, + u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + int err; + + err = qcom_scm_generate_ice_key(lt_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE); + if (err) + return err; + + return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE; +} +EXPORT_SYMBOL_GPL(qcom_ice_generate_key); + +/** + * qcom_ice_prepare_key() - Prepare a wrapped key for inline encryption + * @ice: ICE driver data + * @lt_key: a long-term wrapped key + * @lt_key_size: size of @lt_key in bytes + * @eph_key: output buffer for the ephemerally-wrapped key + * + * Use HWKM to re-wrap a long-term wrapped key with the per-boot ephemeral key. + * + * Return: the size of the resulting wrapped key on success; -EBADMSG if the + * given long-term wrapped key is invalid; or another -errno value. + */ +int qcom_ice_prepare_key(struct qcom_ice *ice, + const u8 *lt_key, size_t lt_key_size, + u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + int err; + + err = qcom_scm_prepare_ice_key(lt_key, lt_key_size, + eph_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE); + if (err == -EIO || err == -EINVAL) + err = -EBADMSG; /* probably invalid key */ + if (err) + return err; + + return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE; +} +EXPORT_SYMBOL_GPL(qcom_ice_prepare_key); + +/** + * qcom_ice_import_key() - Import a raw key for inline encryption + * @ice: ICE driver data + * @raw_key: the raw key to import + * @raw_key_size: size of @raw_key in bytes + * @lt_key: output buffer for the long-term wrapped key + * + * Use HWKM to import a raw key and return it as a long-term wrapped key. + * + * Return: the size of the resulting wrapped key on success; -errno on failure. + */ +int qcom_ice_import_key(struct qcom_ice *ice, + const u8 *raw_key, size_t raw_key_size, + u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) +{ + int err; + + err = qcom_scm_import_ice_key(raw_key, raw_key_size, + lt_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE); + if (err) + return err; + + return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE; +} +EXPORT_SYMBOL_GPL(qcom_ice_import_key); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { @@ -261,7 +570,7 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, * Return: ICE pointer on success, NULL if there is no ICE data provided by the * consumer or ERR_PTR() on error. */ -struct qcom_ice *of_qcom_ice_get(struct device *dev) +static struct qcom_ice *of_qcom_ice_get(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct qcom_ice *ice; @@ -322,7 +631,53 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev) return ice; } -EXPORT_SYMBOL_GPL(of_qcom_ice_get); + +static void qcom_ice_put(const struct qcom_ice *ice) +{ + struct platform_device *pdev = to_platform_device(ice->dev); + + if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice")) + platform_device_put(pdev); +} + +static void devm_of_qcom_ice_put(struct device *dev, void *res) +{ + qcom_ice_put(*(struct qcom_ice **)res); +} + +/** + * devm_of_qcom_ice_get() - Devres managed helper to get an ICE instance from + * a DT node. + * @dev: device pointer for the consumer device. + * + * This function will provide an ICE instance either by creating one for the + * consumer device if its DT node provides the 'ice' reg range and the 'ice' + * clock (for legacy DT style). On the other hand, if consumer provides a + * phandle via 'qcom,ice' property to an ICE DT, the ICE instance will already + * be created and so this function will return that instead. + * + * Return: ICE pointer on success, NULL if there is no ICE data provided by the + * consumer or ERR_PTR() on error. + */ +struct qcom_ice *devm_of_qcom_ice_get(struct device *dev) +{ + struct qcom_ice *ice, **dr; + + dr = devres_alloc(devm_of_qcom_ice_put, sizeof(*dr), GFP_KERNEL); + if (!dr) + return ERR_PTR(-ENOMEM); + + ice = of_qcom_ice_get(dev); + if (!IS_ERR_OR_NULL(ice)) { + *dr = ice; + devres_add(dev, dr); + } else { + devres_free(dr); + } + + return ice; +} +EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get); static int qcom_ice_probe(struct platform_device *pdev) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 56823b6a2fac..192edc3f64dc 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -35,6 +35,11 @@ #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) #define ATTR0_BONUS_WAYS_SHIFT 16 +#define ATTR2_PROBE_TARGET_WAYS_MASK BIT(4) +#define ATTR2_FIXED_SIZE_MASK BIT(8) +#define ATTR2_PRIORITY_MASK GENMASK(14, 12) +#define ATTR2_PARENT_SCID_MASK GENMASK(21, 16) +#define ATTR2_IN_A_GROUP_MASK BIT(24) #define LLCC_STATUS_READ_DELAY 100 #define CACHE_LINE_SIZE_SHIFT 6 @@ -49,6 +54,10 @@ #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) +#define LLCC_V6_TRP_ATTR0_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR0_CFG] + SZ_64 * (n)) +#define LLCC_V6_TRP_ATTR1_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR1_CFG] + SZ_64 * (n)) +#define LLCC_V6_TRP_ATTR2_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR2_CFG] + SZ_64 * (n)) +#define LLCC_V6_TRP_ATTR3_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR3_CFG] + SZ_64 * (n)) #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 @@ -66,6 +75,7 @@ #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 +#define LLCC_VERSION_6_0_0_0 0X06000000 /** * struct llcc_slice_config - Data associated with the llcc slice @@ -106,6 +116,7 @@ * ovcap_en. * @vict_prio: When current scid is under-capacity, allocate over other * lower-than victim priority-line threshold scid. + * @parent_slice_id: For grouped slices, specifies the slice id of the parent. */ struct llcc_slice_config { u32 usecase_id; @@ -130,6 +141,7 @@ struct llcc_slice_config { bool ovcap_en; bool ovcap_prio; bool vict_prio; + u32 parent_slice_id; }; struct qcom_llcc_config { @@ -153,6 +165,21 @@ struct qcom_sct_config { enum llcc_reg_offset { LLCC_COMMON_HW_INFO, LLCC_COMMON_STATUS0, + LLCC_TRP_ATTR0_CFG, + LLCC_TRP_ATTR1_CFG, + LLCC_TRP_ATTR2_CFG, + LLCC_TRP_ATTR3_CFG, + LLCC_TRP_SID_DIS_CAP_ALLOC, + LLCC_TRP_ALGO_STALE_EN, + LLCC_TRP_ALGO_STALE_CAP_EN, + LLCC_TRP_ALGO_MRU0, + LLCC_TRP_ALGO_MRU1, + LLCC_TRP_ALGO_ALLOC0, + LLCC_TRP_ALGO_ALLOC1, + LLCC_TRP_ALGO_ALLOC2, + LLCC_TRP_ALGO_ALLOC3, + LLCC_TRP_WRS_EN, + LLCC_TRP_WRS_CACHEABLE_EN, }; static const struct llcc_slice_config ipq5424_data[] = { @@ -2662,6 +2689,263 @@ static const struct llcc_slice_config sm8650_data[] = { }, }; +static const struct llcc_slice_config sm8750_data[] = { + { + .usecase_id = LLCC_CPUSS, + .slice_id = 1, + .max_cap = 5120, + .priority = 1, + .bonus_ways = 0xffffffff, + .activate_on_init = true, + .write_scid_en = true, + }, { + .usecase_id = LLCC_MDMHPFX, + .slice_id = 24, + .max_cap = 1024, + .priority = 5, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_VIDSC0, + .slice_id = 2, + .max_cap = 512, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_AUDIO, + .slice_id = 35, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_MDMHPGRW, + .slice_id = 25, + .max_cap = 1024, + .priority = 5, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_MODHW, + .slice_id = 26, + .max_cap = 1024, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_CMPT, + .slice_id = 34, + .max_cap = 4096, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_GPUHTW, + .slice_id = 11, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_GPU, + .slice_id = 9, + .max_cap = 5632, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .write_scid_en = true, + .write_scid_cacheable_en = true + }, { + .usecase_id = LLCC_MMUHWT, + .slice_id = 18, + .max_cap = 768, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .activate_on_init = true, + }, { + .usecase_id = LLCC_DISP, + .slice_id = 16, + .max_cap = 7168, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .cache_mode = 2, + .stale_en = true, + }, { + .usecase_id = LLCC_VIDFW, + .slice_id = 17, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_CAMFW, + .slice_id = 20, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_MDMPNG, + .slice_id = 27, + .max_cap = 256, + .priority = 5, + .fixed_size = true, + .bonus_ways = 0xf0000000, + }, { + .usecase_id = LLCC_AUDHW, + .slice_id = 22, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_CVP, + .slice_id = 8, + .max_cap = 800, + .priority = 5, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .vict_prio = true, + }, { + .usecase_id = LLCC_MODPE, + .slice_id = 29, + .max_cap = 256, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xf0000000, + .alloc_oneway_en = true, + }, { + .usecase_id = LLCC_WRCACHE, + .slice_id = 31, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .activate_on_init = true, + }, { + .usecase_id = LLCC_CVPFW, + .slice_id = 19, + .max_cap = 64, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_CMPTHCP, + .slice_id = 15, + .max_cap = 256, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_LCPDARE, + .slice_id = 30, + .max_cap = 128, + .priority = 5, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .activate_on_init = true, + .alloc_oneway_en = true, + }, { + .usecase_id = LLCC_AENPU, + .slice_id = 3, + .max_cap = 3072, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .cache_mode = 2, + }, { + .usecase_id = LLCC_ISLAND1, + .slice_id = 12, + .max_cap = 7936, + .priority = 7, + .fixed_size = true, + .bonus_ways = 0x7fffffff, + }, { + .usecase_id = LLCC_DISP_WB, + .slice_id = 23, + .max_cap = 512, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_VIDVSP, + .slice_id = 4, + .max_cap = 256, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + }, { + .usecase_id = LLCC_VIDDEC, + .slice_id = 5, + .max_cap = 6144, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .cache_mode = 2, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CAMOFE, + .slice_id = 33, + .max_cap = 6144, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .stale_en = true, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CAMRTIP, + .slice_id = 13, + .max_cap = 1024, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .stale_en = true, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CAMSRTIP, + .slice_id = 14, + .max_cap = 6144, + .priority = 4, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .stale_en = true, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CAMRTRF, + .slice_id = 7, + .max_cap = 3584, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .stale_en = true, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CAMSRTRF, + .slice_id = 21, + .max_cap = 6144, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .stale_en = true, + .ovcap_prio = true, + .parent_slice_id = 33, + }, { + .usecase_id = LLCC_CPUSSMPAM, + .slice_id = 6, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xffffffff, + .activate_on_init = true, + .write_scid_en = true, + }, +}; + static const struct llcc_slice_config qcs615_data[] = { { .usecase_id = LLCC_CPUSS, @@ -3161,6 +3445,33 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { .drp_ecc_db_err_syn0 = 0x52120, }; +static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = { + .trp_ecc_error_status0 = 0x47448, + .trp_ecc_error_status1 = 0x47450, + .trp_ecc_sb_err_syn0 = 0x47490, + .trp_ecc_db_err_syn0 = 0x474d0, + .trp_ecc_error_cntr_clear = 0x47444, + .trp_interrupt_0_status = 0x47600, + .trp_interrupt_0_clear = 0x47604, + .trp_interrupt_0_enable = 0x47608, + + /* LLCC Common registers */ + .cmn_status0 = 0x6400c, + .cmn_interrupt_0_enable = 0x6401c, + .cmn_interrupt_2_enable = 0x6403c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg = 0x80000, + .drp_ecc_error_cntr_clear = 0x80004, + .drp_interrupt_status = 0x80020, + .drp_interrupt_clear = 0x80028, + .drp_interrupt_enable = 0x8002c, + .drp_ecc_error_status0 = 0x820f4, + .drp_ecc_error_status1 = 0x820f8, + .drp_ecc_sb_err_syn0 = 0x820fc, + .drp_ecc_db_err_syn0 = 0x82120, +}; + /* LLCC register offset starting from v1.0.0 */ static const u32 llcc_v1_reg_offset[] = { [LLCC_COMMON_HW_INFO] = 0x00030000, @@ -3173,6 +3484,27 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; +/* LLCC register offset starting from v6.0.0 */ +static const u32 llcc_v6_reg_offset[] = { + [LLCC_COMMON_HW_INFO] = 0x00064000, + [LLCC_COMMON_STATUS0] = 0x0006400c, + [LLCC_TRP_ATTR0_CFG] = 0x00041000, + [LLCC_TRP_ATTR1_CFG] = 0x00041008, + [LLCC_TRP_ATTR2_CFG] = 0x00041010, + [LLCC_TRP_ATTR3_CFG] = 0x00041014, + [LLCC_TRP_SID_DIS_CAP_ALLOC] = 0x00042000, + [LLCC_TRP_ALGO_STALE_EN] = 0x00042008, + [LLCC_TRP_ALGO_STALE_CAP_EN] = 0x00042010, + [LLCC_TRP_ALGO_MRU0] = 0x00042018, + [LLCC_TRP_ALGO_MRU1] = 0x00042020, + [LLCC_TRP_ALGO_ALLOC0] = 0x00042028, + [LLCC_TRP_ALGO_ALLOC1] = 0x00042030, + [LLCC_TRP_ALGO_ALLOC2] = 0x00042038, + [LLCC_TRP_ALGO_ALLOC3] = 0x00042040, + [LLCC_TRP_WRS_EN] = 0x00042080, + [LLCC_TRP_WRS_CACHEABLE_EN] = 0x00042088, +}; + static const struct qcom_llcc_config qcs615_cfg[] = { { .sct_data = qcs615_data, @@ -3379,6 +3711,16 @@ static const struct qcom_llcc_config sm8650_cfg[] = { }, }; +static const struct qcom_llcc_config sm8750_cfg[] = { + { + .sct_data = sm8750_data, + .size = ARRAY_SIZE(sm8750_data), + .skip_llcc_cfg = false, + .reg_offset = llcc_v6_reg_offset, + .edac_reg_offset = &llcc_v6_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config x1e80100_cfg[] = { { .sct_data = x1e80100_data, @@ -3489,6 +3831,11 @@ static const struct qcom_sct_config sm8650_cfgs = { .num_config = ARRAY_SIZE(sm8650_cfg), }; +static const struct qcom_sct_config sm8750_cfgs = { + .llcc_config = sm8750_cfg, + .num_config = ARRAY_SIZE(sm8750_cfg), +}; + static const struct qcom_sct_config x1e80100_cfgs = { .llcc_config = x1e80100_cfg, .num_config = ARRAY_SIZE(x1e80100_cfg), @@ -3869,6 +4216,139 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } +static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config, + const struct qcom_llcc_config *cfg) +{ + u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover; + u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio; + u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg; + u32 attr0_val, attr1_val, attr2_val, attr3_val; + u32 slice_offset, reg_offset; + struct llcc_slice_desc *desc; + u32 wren, wr_cache_en; + int ret; + + attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id); + attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id); + attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id); + attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id); + + attr0_val = config->res_ways; + attr1_val = config->bonus_ways; + attr2_val = config->cache_mode; + attr2_val |= FIELD_PREP(ATTR2_PROBE_TARGET_WAYS_MASK, config->probe_target_ways); + attr2_val |= FIELD_PREP(ATTR2_FIXED_SIZE_MASK, config->fixed_size); + attr2_val |= FIELD_PREP(ATTR2_PRIORITY_MASK, config->priority); + + if (config->parent_slice_id && config->fixed_size) { + attr2_val |= FIELD_PREP(ATTR2_PARENT_SCID_MASK, config->parent_slice_id); + attr2_val |= ATTR2_IN_A_GROUP_MASK; + } + + attr3_val = MAX_CAP_TO_BYTES(config->max_cap); + attr3_val /= drv_data->num_banks; + attr3_val >>= CACHE_LINE_SIZE_SHIFT; + + ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); + if (ret) + return ret; + + ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); + if (ret) + return ret; + + ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); + if (ret) + return ret; + + ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val); + if (ret) + return ret; + + slice_offset = config->slice_id % 32; + reg_offset = (config->slice_id / 32) * 4; + + wren = config->write_scid_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_WRS_EN] + reg_offset, + BIT(slice_offset), wren); + if (ret) + return ret; + + wr_cache_en = config->write_scid_cacheable_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_WRS_CACHEABLE_EN] + reg_offset, + BIT(slice_offset), wr_cache_en); + if (ret) + return ret; + + stale_en = config->stale_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_STALE_EN] + reg_offset, + BIT(slice_offset), stale_en); + if (ret) + return ret; + + stale_cap_en = config->stale_cap_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_STALE_CAP_EN] + reg_offset, + BIT(slice_offset), stale_cap_en); + if (ret) + return ret; + + mru_uncap_en = config->mru_uncap_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_MRU0] + reg_offset, + BIT(slice_offset), mru_uncap_en); + if (ret) + return ret; + + mru_rollover = config->mru_rollover << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_MRU1] + reg_offset, + BIT(slice_offset), mru_rollover); + if (ret) + return ret; + + alloc_oneway_en = config->alloc_oneway_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC0] + reg_offset, + BIT(slice_offset), alloc_oneway_en); + if (ret) + return ret; + + ovcap_en = config->ovcap_en << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC1] + reg_offset, + BIT(slice_offset), ovcap_en); + if (ret) + return ret; + + ovcap_prio = config->ovcap_prio << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC2] + reg_offset, + BIT(slice_offset), ovcap_prio); + if (ret) + return ret; + + vict_prio = config->vict_prio << slice_offset; + ret = regmap_update_bits(drv_data->bcast_regmap, + cfg->reg_offset[LLCC_TRP_ALGO_ALLOC3] + reg_offset, + BIT(slice_offset), vict_prio); + if (ret) + return ret; + + if (config->activate_on_init) { + desc = llcc_slice_getd(config->usecase_id); + if (PTR_ERR_OR_ZERO(desc)) + return -EINVAL; + + ret = llcc_slice_activate(desc); + } + + return ret; +} + static int qcom_llcc_cfg_program(struct platform_device *pdev, const struct qcom_llcc_config *cfg) { @@ -3880,10 +4360,18 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, sz = drv_data->cfg_size; llcc_table = drv_data->cfg; - for (i = 0; i < sz; i++) { - ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); - if (ret) - return ret; + if (drv_data->version >= LLCC_VERSION_6_0_0_0) { + for (i = 0; i < sz; i++) { + ret = _qcom_llcc_cfg_program_v6(&llcc_table[i], cfg); + if (ret) + return ret; + } + } else { + for (i = 0; i < sz; i++) { + ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); + if (ret) + return ret; + } } return ret; @@ -4102,6 +4590,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs }, { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs }, { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs }, + { .compatible = "qcom,sm8750-llcc", .data = &sm8750_cfgs }, { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs }, { } }; diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c index 328b6153b2be..71be378d2e43 100644 --- a/drivers/soc/qcom/pdr_interface.c +++ b/drivers/soc/qcom/pdr_interface.c @@ -75,7 +75,6 @@ static int pdr_locator_new_server(struct qmi_handle *qmi, { struct pdr_handle *pdr = container_of(qmi, struct pdr_handle, locator_hdl); - struct pdr_service *pds; mutex_lock(&pdr->lock); /* Create a local client port for QMI communication */ @@ -87,12 +86,7 @@ static int pdr_locator_new_server(struct qmi_handle *qmi, mutex_unlock(&pdr->lock); /* Service pending lookup requests */ - mutex_lock(&pdr->list_lock); - list_for_each_entry(pds, &pdr->lookups, node) { - if (pds->need_locator_lookup) - schedule_work(&pdr->locator_work); - } - mutex_unlock(&pdr->list_lock); + schedule_work(&pdr->locator_work); return 0; } diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h index 8d17f7fb79e7..039508c1bbf7 100644 --- a/drivers/soc/qcom/pdr_internal.h +++ b/drivers/soc/qcom/pdr_internal.h @@ -91,7 +91,6 @@ struct servreg_loc_pfr_resp { struct qmi_response_type_v01 rsp; }; -extern const struct qmi_elem_info servreg_location_entry_ei[]; extern const struct qmi_elem_info servreg_get_domain_list_req_ei[]; extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[]; extern const struct qmi_elem_info servreg_register_listener_req_ei[]; diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 052c292eeda6..0a6d325b195c 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -233,7 +233,7 @@ static void pmic_glink_pdr_callback(int state, char *svc_path, void *priv) static int pmic_glink_rpmsg_probe(struct rpmsg_device *rpdev) { - struct pmic_glink *pg = __pmic_glink; + struct pmic_glink *pg; guard(mutex)(&__pmic_glink_lock); pg = __pmic_glink; @@ -371,15 +371,11 @@ static void pmic_glink_remove(struct platform_device *pdev) __pmic_glink = NULL; } -static const unsigned long pmic_glink_sc8280xp_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | - BIT(PMIC_GLINK_CLIENT_ALTMODE); - static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | BIT(PMIC_GLINK_CLIENT_ALTMODE) | BIT(PMIC_GLINK_CLIENT_UCSI); static const struct of_device_id pmic_glink_of_match[] = { - { .compatible = "qcom,sc8280xp-pmic-glink", .data = &pmic_glink_sc8280xp_client_mask }, { .compatible = "qcom,pmic-glink", .data = &pmic_glink_sm8450_client_mask }, {} }; diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index bd06ce161804..7f11acd33323 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -218,21 +218,29 @@ static void pmic_glink_altmode_worker(struct work_struct *work) { struct pmic_glink_altmode_port *alt_port = work_to_altmode_port(work); struct pmic_glink_altmode *altmode = alt_port->altmode; + enum drm_connector_status conn_status; typec_switch_set(alt_port->typec_switch, alt_port->orientation); - if (alt_port->svid == USB_TYPEC_DP_SID && alt_port->mode == 0xff) - pmic_glink_altmode_safe(altmode, alt_port); - else if (alt_port->svid == USB_TYPEC_DP_SID) - pmic_glink_altmode_enable_dp(altmode, alt_port, alt_port->mode, - alt_port->hpd_state, alt_port->hpd_irq); - else - pmic_glink_altmode_enable_usb(altmode, alt_port); + if (alt_port->svid == USB_TYPEC_DP_SID) { + if (alt_port->mode == 0xff) { + pmic_glink_altmode_safe(altmode, alt_port); + } else { + pmic_glink_altmode_enable_dp(altmode, alt_port, + alt_port->mode, + alt_port->hpd_state, + alt_port->hpd_irq); + } - drm_aux_hpd_bridge_notify(&alt_port->bridge->dev, - alt_port->hpd_state ? - connector_status_connected : - connector_status_disconnected); + if (alt_port->hpd_state) + conn_status = connector_status_connected; + else + conn_status = connector_status_disconnected; + + drm_aux_hpd_bridge_notify(&alt_port->bridge->dev, conn_status); + } else { + pmic_glink_altmode_enable_usb(altmode, alt_port); + } pmic_glink_altmode_request(altmode, ALTMODE_PAN_ACK, alt_port->index); } diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 0320ad3b9148..a543ab9bee6c 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -12,6 +12,7 @@ #include <linux/platform_device.h> #include <linux/thermal.h> #include <linux/slab.h> +#include <linux/string_choices.h> #include <linux/soc/qcom/qcom_aoss.h> #define CREATE_TRACE_POINTS @@ -358,7 +359,7 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, return 0; ret = qmp_send(qmp_cdev->qmp, "{class: volt_flr, event:zero_temp, res:%s, value:%s}", - qmp_cdev->name, cdev_state ? "on" : "off"); + qmp_cdev->name, str_on_off(cdev_state)); if (!ret) qmp_cdev->state = cdev_state; diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index 154ca5beb471..3abea241b1c4 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -429,6 +429,16 @@ static const struct qcom_pdm_domain_data *sc8280xp_domains[] = { NULL, }; +/* Unlike SDM660, SDM630/636 lack CDSP */ +static const struct qcom_pdm_domain_data *sdm630_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &adsp_sensor_pd, + &mpss_root_pd, + &mpss_wlan_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sdm660_domains[] = { &adsp_audio_pd, &adsp_root_pd, @@ -478,6 +488,16 @@ static const struct qcom_pdm_domain_data *sm6350_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *sm7150_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &adsp_sensor_pd, + &cdsp_root_pd, + &mpss_root_pd_gps, + &mpss_wlan_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sm8150_domains[] = { &adsp_audio_pd, &adsp_root_pd, @@ -546,6 +566,8 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,sc7280", .data = sc7280_domains, }, { .compatible = "qcom,sc8180x", .data = sc8180x_domains, }, { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, }, + { .compatible = "qcom,sdm630", .data = sdm630_domains, }, + { .compatible = "qcom,sdm636", .data = sdm630_domains, }, { .compatible = "qcom,sda660", .data = sdm660_domains, }, { .compatible = "qcom,sdm660", .data = sdm660_domains, }, { .compatible = "qcom,sdm670", .data = sdm670_domains, }, @@ -553,6 +575,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,sm4250", .data = sm6115_domains, }, { .compatible = "qcom,sm6115", .data = sm6115_domains, }, { .compatible = "qcom,sm6350", .data = sm6350_domains, }, + { .compatible = "qcom,sm7150", .data = sm7150_domains, }, { .compatible = "qcom,sm7225", .data = sm6350_domains, }, { .compatible = "qcom,sm7325", .data = sc7280_domains, }, { .compatible = "qcom,sm8150", .data = sm8150_domains, }, diff --git a/drivers/soc/qcom/qcom_pdr_msg.c b/drivers/soc/qcom/qcom_pdr_msg.c index bf3e4a47165e..ca98932140d8 100644 --- a/drivers/soc/qcom/qcom_pdr_msg.c +++ b/drivers/soc/qcom/qcom_pdr_msg.c @@ -8,7 +8,7 @@ #include "pdr_internal.h" -const struct qmi_elem_info servreg_location_entry_ei[] = { +static const struct qmi_elem_info servreg_location_entry_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -47,7 +47,6 @@ const struct qmi_elem_info servreg_location_entry_ei[] = { }, {} }; -EXPORT_SYMBOL_GPL(servreg_location_entry_ei); const struct qmi_elem_info servreg_get_domain_list_req_ei[] = { { diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 592819701809..cf425930539e 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -86,7 +86,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 20 +#define SMEM_HOST_COUNT 25 /** * struct smem_proc_comm - proc_comm communication struct (legacy) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index a3e88ced328a..cb515c2340c1 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -399,7 +399,7 @@ static int qcom_smp2p_inbound_entry(struct qcom_smp2p *smp2p, struct smp2p_entry *entry, struct device_node *node) { - entry->domain = irq_domain_add_linear(node, 32, &smp2p_irq_ops, entry); + entry->domain = irq_domain_create_linear(of_fwnode_handle(node), 32, &smp2p_irq_ops, entry); if (!entry->domain) { dev_err(smp2p->dev, "failed to add irq_domain\n"); return -ENOMEM; @@ -575,7 +575,7 @@ static int qcom_smp2p_probe(struct platform_device *pdev) smp2p->mbox_client.knows_txdone = true; smp2p->mbox_chan = mbox_request_channel(&smp2p->mbox_client, 0); if (IS_ERR(smp2p->mbox_chan)) { - if (PTR_ERR(smp2p->mbox_chan) != -ENODEV) + if (PTR_ERR(smp2p->mbox_chan) != -ENOENT) return PTR_ERR(smp2p->mbox_chan); smp2p->mbox_chan = NULL; diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index e803ea342c97..021e9d1f61dc 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -456,7 +456,7 @@ static int smsm_inbound_entry(struct qcom_smsm *smsm, return ret; } - entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry); + entry->domain = irq_domain_create_linear(of_fwnode_handle(node), 32, &smsm_irq_ops, entry); if (!entry->domain) { dev_err(smsm->dev, "failed to add irq_domain\n"); return -ENOMEM; diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 18d7f1be9093..8c4147737c35 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -444,6 +444,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ5302) }, { qcom_board_id(QCS8550) }, { qcom_board_id(QCM8550) }, + { qcom_board_id(SM8750) }, { qcom_board_id(IPQ5300) }, { qcom_board_id(IPQ5321) }, { qcom_board_id(IPQ5424) }, diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 6d2e135eed89..fbc3b69d21a7 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -65,17 +65,20 @@ if ARM && ARCH_RENESAS config ARCH_EMEV2 bool "ARM32 Platform support for Emma Mobile EV2" + default ARCH_RENESAS select HAVE_ARM_SCU if SMP select SYS_SUPPORTS_EM_STI config ARCH_R8A7794 bool "ARM32 Platform support for R-Car E2" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_814220 select SYSC_R8A7794 config ARCH_R8A7779 bool "ARM32 Platform support for R-Car H1" + default ARCH_RENESAS select ARCH_RCAR_GEN1 select ARM_ERRATA_754322 select ARM_GLOBAL_TIMER @@ -85,6 +88,7 @@ config ARCH_R8A7779 config ARCH_R8A7790 bool "ARM32 Platform support for R-Car H2" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select ARM_ERRATA_814220 @@ -93,11 +97,13 @@ config ARCH_R8A7790 config ARCH_R8A7778 bool "ARM32 Platform support for R-Car M1A" + default ARCH_RENESAS select ARCH_RCAR_GEN1 select ARM_ERRATA_754322 config ARCH_R8A7793 bool "ARM32 Platform support for R-Car M2-N" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select I2C @@ -105,6 +111,7 @@ config ARCH_R8A7793 config ARCH_R8A7791 bool "ARM32 Platform support for R-Car M2-W" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select I2C @@ -112,18 +119,21 @@ config ARCH_R8A7791 config ARCH_R8A7792 bool "ARM32 Platform support for R-Car V2H" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select SYSC_R8A7792 config ARCH_R8A7740 bool "ARM32 Platform support for R-Mobile A1" + default ARCH_RENESAS select ARCH_RMOBILE select ARM_ERRATA_754322 select RENESAS_INTC_IRQPIN config ARCH_R8A73A4 bool "ARM32 Platform support for R-Mobile APE6" + default ARCH_RENESAS select ARCH_RMOBILE select ARM_ERRATA_798181 if SMP select ARM_ERRATA_814220 @@ -132,6 +142,7 @@ config ARCH_R8A73A4 config ARCH_R7S72100 bool "ARM32 Platform support for RZ/A1H" + default ARCH_RENESAS select ARM_ERRATA_754322 select PM select PM_GENERIC_DOMAINS @@ -141,6 +152,7 @@ config ARCH_R7S72100 config ARCH_R7S9210 bool "ARM32 Platform support for RZ/A2" + default ARCH_RENESAS select PM select PM_GENERIC_DOMAINS select RENESAS_OSTM @@ -148,18 +160,21 @@ config ARCH_R7S9210 config ARCH_R8A77470 bool "ARM32 Platform support for RZ/G1C" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_814220 select SYSC_R8A77470 config ARCH_R8A7745 bool "ARM32 Platform support for RZ/G1E" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_814220 select SYSC_R8A7745 config ARCH_R8A7742 bool "ARM32 Platform support for RZ/G1H" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select ARM_ERRATA_814220 @@ -167,23 +182,27 @@ config ARCH_R8A7742 config ARCH_R8A7743 bool "ARM32 Platform support for RZ/G1M" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select SYSC_R8A7743 config ARCH_R8A7744 bool "ARM32 Platform support for RZ/G1N" + default ARCH_RENESAS select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP select SYSC_R8A7743 config ARCH_R9A06G032 bool "ARM32 Platform support for RZ/N1D" + default ARCH_RENESAS select ARCH_RZN1 select ARM_ERRATA_814220 config ARCH_SH73A0 bool "ARM32 Platform support for SH-Mobile AG5" + default ARCH_RENESAS select ARCH_RMOBILE select ARM_ERRATA_754322 select ARM_GLOBAL_TIMER @@ -197,6 +216,7 @@ if ARM64 config ARCH_R8A77995 bool "ARM64 Platform support for R-Car D3" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77995 help @@ -205,6 +225,7 @@ config ARCH_R8A77995 config ARCH_R8A77990 bool "ARM64 Platform support for R-Car E3" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77990 help @@ -213,6 +234,7 @@ config ARCH_R8A77990 config ARCH_R8A77951 bool "ARM64 Platform support for R-Car H3 ES2.0+" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A7795 help @@ -222,6 +244,7 @@ config ARCH_R8A77951 config ARCH_R8A77965 bool "ARM64 Platform support for R-Car M3-N" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77965 help @@ -230,6 +253,7 @@ config ARCH_R8A77965 config ARCH_R8A77960 bool "ARM64 Platform support for R-Car M3-W" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77960 help @@ -237,6 +261,7 @@ config ARCH_R8A77960 config ARCH_R8A77961 bool "ARM64 Platform support for R-Car M3-W+" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77961 help @@ -245,6 +270,7 @@ config ARCH_R8A77961 config ARCH_R8A779F0 bool "ARM64 Platform support for R-Car S4-8" + default y if ARCH_RENESAS select ARCH_RCAR_GEN4 select SYSC_R8A779F0 help @@ -252,6 +278,7 @@ config ARCH_R8A779F0 config ARCH_R8A77980 bool "ARM64 Platform support for R-Car V3H" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77980 help @@ -259,6 +286,7 @@ config ARCH_R8A77980 config ARCH_R8A77970 bool "ARM64 Platform support for R-Car V3M" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A77970 help @@ -266,6 +294,7 @@ config ARCH_R8A77970 config ARCH_R8A779A0 bool "ARM64 Platform support for R-Car V3U" + default y if ARCH_RENESAS select ARCH_RCAR_GEN4 select SYSC_R8A779A0 help @@ -273,6 +302,7 @@ config ARCH_R8A779A0 config ARCH_R8A779G0 bool "ARM64 Platform support for R-Car V4H" + default y if ARCH_RENESAS select ARCH_RCAR_GEN4 select SYSC_R8A779G0 help @@ -280,6 +310,7 @@ config ARCH_R8A779G0 config ARCH_R8A779H0 bool "ARM64 Platform support for R-Car V4M" + default y if ARCH_RENESAS select ARCH_RCAR_GEN4 select SYSC_R8A779H0 help @@ -287,6 +318,7 @@ config ARCH_R8A779H0 config ARCH_R8A774C0 bool "ARM64 Platform support for RZ/G2E" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A774C0 help @@ -294,6 +326,7 @@ config ARCH_R8A774C0 config ARCH_R8A774E1 bool "ARM64 Platform support for RZ/G2H" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A774E1 help @@ -301,6 +334,7 @@ config ARCH_R8A774E1 config ARCH_R8A774A1 bool "ARM64 Platform support for RZ/G2M" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A774A1 help @@ -308,6 +342,7 @@ config ARCH_R8A774A1 config ARCH_R8A774B1 bool "ARM64 Platform support for RZ/G2N" + default y if ARCH_RENESAS select ARCH_RCAR_GEN3 select SYSC_R8A774B1 help @@ -315,30 +350,36 @@ config ARCH_R8A774B1 config ARCH_R9A07G043 bool "ARM64 Platform support for RZ/G2UL" + default y if ARCH_RENESAS select ARCH_RZG2L help This enables support for the Renesas RZ/G2UL SoC variants. config ARCH_R9A07G044 bool "ARM64 Platform support for RZ/G2L" + default y if ARCH_RENESAS select ARCH_RZG2L help This enables support for the Renesas RZ/G2L SoC variants. config ARCH_R9A07G054 bool "ARM64 Platform support for RZ/V2L" + default y if ARCH_RENESAS select ARCH_RZG2L help This enables support for the Renesas RZ/V2L SoC variants. config ARCH_R9A08G045 bool "ARM64 Platform support for RZ/G3S" + default y if ARCH_RENESAS select ARCH_RZG2L + select SYSC_R9A08G045 help This enables support for the Renesas RZ/G3S SoC variants. config ARCH_R9A09G011 bool "ARM64 Platform support for RZ/V2M" + default y if ARCH_RENESAS select PM select PM_GENERIC_DOMAINS select PWC_RZV2M @@ -347,12 +388,23 @@ config ARCH_R9A09G011 config ARCH_R9A09G047 bool "ARM64 Platform support for RZ/G3E" + default y if ARCH_RENESAS + select SYS_R9A09G047 help This enables support for the Renesas RZ/G3E SoC variants. +config ARCH_R9A09G056 + bool "ARM64 Platform support for RZ/V2N" + default y if ARCH_RENESAS + select SYS_R9A09G056 + help + This enables support for the Renesas RZ/V2N SoC variants. + config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" + default y if ARCH_RENESAS select RENESAS_RZV2H_ICU + select SYS_R9A09G057 help This enables support for the Renesas RZ/V2H(P) SoC variants. @@ -383,4 +435,23 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST +config SYSC_RZ + bool "System controller for RZ SoCs" if COMPILE_TEST + +config SYSC_R9A08G045 + bool "Renesas RZ/G3S System controller support" if COMPILE_TEST + select SYSC_RZ + +config SYS_R9A09G047 + bool "Renesas RZ/G3E System controller support" if COMPILE_TEST + select SYSC_RZ + +config SYS_R9A09G056 + bool "Renesas RZ/V2N System controller support" if COMPILE_TEST + select SYSC_RZ + +config SYS_R9A09G057 + bool "Renesas RZ/V2H System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..3bdcc6a395d5 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,7 +6,12 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o +obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o +obj-$(CONFIG_SYS_R9A09G056) += r9a09g056-sys.o +obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o +obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c new file mode 100644 index 000000000000..f4db1431e036 --- /dev/null +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <linux/bits.h> +#include <linux/init.h> + +#include "rz-sysc.h" + +static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { + .family = "RZ/G3S", + .id = 0x85e0447, + .devid_offset = 0xa04, + .revision_mask = GENMASK(31, 28), + .specific_id_mask = GENMASK(27, 0), +}; + +const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = { + .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c new file mode 100644 index 000000000000..cd2eb7782cfe --- /dev/null +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3E System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/io.h> + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_CA55_DIS BIT(8) +#define SYS_LSI_PRR_NPU_DIS BIT(1) + +static void rzg3e_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + bool is_quad_core, npu_enabled; + u32 prr_val, mode_val; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check CPU and NPU configuration */ + is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS); + npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS); + + dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n", + is_quad_core ? "Quad" : "Dual", soc_dev_attr->family, + soc_dev_attr->soc_id, soc_dev_attr->revision, + npu_enabled ? " with Ethos-U55" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = { + .family = "RZ/G3E", + .id = 0x8679447, + .devid_offset = 0x304, + .revision_mask = GENMASK(31, 28), + .specific_id_mask = GENMASK(27, 0), + .print_id = rzg3e_sys_print_id, +}; + +const struct rz_sysc_init_data rzg3e_sys_init_data = { + .soc_id_init_data = &rzg3e_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c new file mode 100644 index 000000000000..3ad1422eba36 --- /dev/null +++ b/drivers/soc/renesas/r9a09g056-sys.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2N System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/io.h> + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +#define SYS_LSI_MODE_SEC_EN BIT(16) +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +#define SYS_RZV2N_FEATURE_G31 BIT(0) +#define SYS_RZV2N_FEATURE_C55 BIT(1) +#define SYS_RZV2N_FEATURE_SEC BIT(2) + +static void rzv2n_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + u32 prr_val, mode_val; + u8 feature_flags; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU, ISP and Cryptographic configuration */ + feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0; + feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0; + feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0; + + dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision, + feature_flags ? " with" : "", + feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "", + feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "", + feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = { + .family = "RZ/V2N", + .id = 0x867d447, + .devid_offset = 0x304, + .revision_mask = GENMASK(31, 28), + .specific_id_mask = GENMASK(27, 0), + .print_id = rzv2n_sys_print_id, +}; + +const struct rz_sysc_init_data rzv2n_sys_init_data = { + .soc_id_init_data = &rzv2n_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c new file mode 100644 index 000000000000..4c21cc29edbc --- /dev/null +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2H System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/io.h> + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +static void rzv2h_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + bool gpu_enabled, isp_enabled; + u32 prr_val, mode_val; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU and ISP configuration */ + gpu_enabled = !(prr_val & SYS_LSI_PRR_GPU_DIS); + isp_enabled = !(prr_val & SYS_LSI_PRR_ISP_DIS); + + dev_info(dev, "Detected Renesas %s %s Rev %s%s%s\n", + soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision, + gpu_enabled ? " with GE3D (Mali-G31)" : "", + isp_enabled ? " with ISP (Mali-C55)" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = { + .family = "RZ/V2H", + .id = 0x847a447, + .devid_offset = 0x304, + .revision_mask = GENMASK(31, 28), + .specific_id_mask = GENMASK(27, 0), + .print_id = rzv2h_sys_print_id, +}; + +const struct rz_sysc_init_data rzv2h_sys_init_data = { + .soc_id_init_data = &rzv2h_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 172d59e6fbcf..df2b38417b80 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,14 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { - .name = "RZ/G3S", -}; - -static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { - .name = "RZ/V2H", -}; - static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; @@ -176,16 +168,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { - .family = &fam_rzg3s, - .id = 0x85e0447, -}; - -static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { - .family = &fam_rzv2h, - .id = 0x847a447, -}; - static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .family = &fam_rzv2l, .id = 0x8447447, @@ -289,7 +271,6 @@ static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { .id = 0x37, }; - static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R7S72100 { .compatible = "renesas,r7s72100", .data = &soc_rz_a1h }, @@ -410,15 +391,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#ifdef CONFIG_ARCH_R9A08G045 - { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, -#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif -#ifdef CONFIG_ARCH_R9A09G057 - { .compatible = "renesas,r9a09g057", .data = &soc_rz_v2h }, -#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -444,11 +419,6 @@ static const struct renesas_id id_rzg2l __initconst = { .mask = 0xfffffff, }; -static const struct renesas_id id_rzv2h __initconst = { - .offset = 0x304, - .mask = 0xfffffff, -}; - static const struct renesas_id id_rzv2m __initconst = { .offset = 0x104, .mask = 0xff, @@ -466,7 +436,6 @@ static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m }, - { .compatible = "renesas,r9a09g057-sys", .data = &id_rzv2h }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; @@ -531,7 +500,7 @@ static int __init renesas_soc_init(void) eslo = product & 0xf; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, eslo); - } else if (id == &id_rzg2l || id == &id_rzv2h) { + } else if (id == &id_rzg2l) { eshi = ((product >> 28) & 0x0f); soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", eshi); diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c new file mode 100644 index 000000000000..ffa65fb4dade --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/sys_soc.h> + +#include "rz-sysc.h" + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + +/** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address + * @dev: SYSC device pointer + */ +struct rz_sysc { + void __iomem *base; + struct device *dev; +}; + +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match) +{ + const struct rz_sysc_init_data *sysc_data = match->data; + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; + struct soc_device_attribute *soc_dev_attr; + const char *soc_id_start, *soc_id_end; + u32 val, revision, specific_id; + struct soc_device *soc_dev; + char soc_id[32] = {0}; + size_t size; + + soc_id_start = strchr(match->compatible, ',') + 1; + soc_id_end = strchr(match->compatible, '-'); + size = soc_id_end - soc_id_start + 1; + if (size > 32) + size = sizeof(soc_id); + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = devm_kstrdup(sysc->dev, soc_data->family, GFP_KERNEL); + if (!soc_dev_attr->family) + return -ENOMEM; + + soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + val = readl(sysc->base + soc_data->devid_offset); + revision = field_get(soc_data->revision_mask, val); + specific_id = field_get(soc_data->specific_id_mask, val); + soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision); + if (!soc_dev_attr->revision) + return -ENOMEM; + + if (soc_data->id && specific_id != soc_data->id) { + dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id); + return -ENODEV; + } + + /* Try to call SoC-specific device identification */ + if (soc_data->print_id) { + soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr); + } else { + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", + soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision); + } + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + return 0; +} + +static const struct of_device_id rz_sysc_match[] = { +#ifdef CONFIG_SYSC_R9A08G045 + { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif +#ifdef CONFIG_SYS_R9A09G047 + { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data }, +#endif +#ifdef CONFIG_SYS_R9A09G056 + { .compatible = "renesas,r9a09g056-sys", .data = &rzv2n_sys_init_data }, +#endif +#ifdef CONFIG_SYS_R9A09G057 + { .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data }, +#endif + { } +}; +MODULE_DEVICE_TABLE(of, rz_sysc_match); + +static int rz_sysc_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct rz_sysc *sysc; + + match = of_match_node(rz_sysc_match, dev->of_node); + if (!match) + return -ENODEV; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + return rz_sysc_soc_init(sysc, match); +} + +static struct platform_driver rz_sysc_driver = { + .driver = { + .name = "renesas-rz-sysc", + .suppress_bind_attrs = true, + .of_match_table = rz_sysc_match + }, + .probe = rz_sysc_probe +}; + +static int __init rz_sysc_init(void) +{ + return platform_driver_register(&rz_sysc_driver); +} +subsys_initcall(rz_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h new file mode 100644 index 000000000000..56bc047a1bff --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ System Controller + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __SOC_RENESAS_RZ_SYSC_H__ +#define __SOC_RENESAS_RZ_SYSC_H__ + +#include <linux/device.h> +#include <linux/sys_soc.h> +#include <linux/types.h> + +/** + * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data + * @family: RZ SoC family + * @id: RZ SoC expected ID + * @devid_offset: SYSC SoC ID register offset + * @revision_mask: SYSC SoC ID revision mask + * @specific_id_mask: SYSC SoC ID specific ID mask + * @print_id: print SoC-specific extended device identification + */ +struct rz_sysc_soc_id_init_data { + const char * const family; + u32 id; + u32 devid_offset; + u32 revision_mask; + u32 specific_id_mask; + void (*print_id)(struct device *dev, void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr); +}; + +/** + * struct rz_sysc_init_data - RZ SYSC initialization data + * @soc_id_init_data: RZ SYSC SoC ID initialization data + */ +struct rz_sysc_init_data { + const struct rz_sysc_soc_id_init_data *soc_id_init_data; +}; + +extern const struct rz_sysc_init_data rzg3e_sys_init_data; +extern const struct rz_sysc_init_data rzg3s_sysc_init_data; +extern const struct rz_sysc_init_data rzv2h_sys_init_data; +extern const struct rz_sysc_init_data rzv2n_sys_init_data; + +#endif /* __SOC_RENESAS_RZ_SYSC_H__ */ diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c index 97006cc3b946..8e681f519526 100644 --- a/drivers/soc/samsung/exynos-asv.c +++ b/drivers/soc/samsung/exynos-asv.c @@ -9,6 +9,7 @@ * Samsung Exynos SoC Adaptive Supply Voltage support */ +#include <linux/array_size.h> #include <linux/cpu.h> #include <linux/device.h> #include <linux/energy_model.h> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index e37dde1fb588..c86f1058ceed 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -12,6 +12,7 @@ * Samsung Exynos SoC Adaptive Supply Voltage and Chip ID support */ +#include <linux/array_size.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/mfd/syscon.h> @@ -55,7 +56,9 @@ static const struct exynos_soc_id { { "EXYNOS5440", 0xE5440000 }, { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, + { "EXYNOS7870", 0xE7870000 }, /* Compatible with: samsung,exynos850-chipid */ + { "EXYNOS2200", 0xE9925000 }, { "EXYNOS7885", 0xE7885000 }, { "EXYNOS850", 0xE3830000 }, { "EXYNOS8895", 0xE8895000 }, @@ -134,6 +137,8 @@ static int exynos_chipid_probe(struct platform_device *pdev) soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%x", soc_info.revision); + if (!soc_dev_attr->revision) + return -ENOMEM; soc_dev_attr->soc_id = product_id_to_soc_id(soc_info.product_id); if (!soc_dev_attr->soc_id) { pr_err("Unknown SoC\n"); diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index dd5256e5aae1..a77288f49d24 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -5,7 +5,9 @@ // // Exynos - CPU PMU(Power Management Unit) support +#include <linux/array_size.h> #include <linux/arm-smccc.h> +#include <linux/cpuhotplug.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/mfd/core.h> @@ -32,6 +34,7 @@ struct exynos_pmu_context { struct device *dev; const struct exynos_pmu_data *pmu_data; struct regmap *pmureg; + struct regmap *pmuintrgen; }; void __iomem *pmu_base_addr; @@ -221,7 +224,8 @@ static const struct regmap_config regmap_smccfg = { }; static const struct exynos_pmu_data gs101_pmu_data = { - .pmu_secure = true + .pmu_secure = true, + .pmu_cpuhp = true, }; /* @@ -325,6 +329,59 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np, } EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); +/* + * CPU_INFORM register hint values which are used by + * EL3 firmware (el3mon). + */ +#define CPU_INFORM_CLEAR 0 +#define CPU_INFORM_C2 1 + +static int gs101_cpuhp_pmu_online(unsigned int cpu) +{ + unsigned int cpuhint = smp_processor_id(); + u32 reg, mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint), + CPU_INFORM_CLEAR); + + mask = BIT(cpu); + + regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR, + reg & mask); + + return 0; +} + +static int gs101_cpuhp_pmu_offline(unsigned int cpu) +{ + u32 reg, mask; + unsigned int cpuhint = smp_processor_id(); + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint), + CPU_INFORM_C2); + + mask = BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + reg & mask); + + mask = (BIT(cpu + 8)); + regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + reg & mask); + return 0; +} + static int exynos_pmu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -377,6 +434,26 @@ static int exynos_pmu_probe(struct platform_device *pdev) pmu_context->pmureg = regmap; pmu_context->dev = dev; + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) { + pmu_context->pmuintrgen = syscon_regmap_lookup_by_phandle(dev->of_node, + "google,pmu-intr-gen-syscon"); + if (IS_ERR(pmu_context->pmuintrgen)) { + /* + * To maintain support for older DTs that didn't specify syscon phandle + * just issue a warning rather than fail to probe. + */ + dev_warn(&pdev->dev, "pmu-intr-gen syscon unavailable\n"); + } else { + cpuhp_setup_state(CPUHP_BP_PREPARE_DYN, + "soc/exynos-pmu:prepare", + gs101_cpuhp_pmu_online, NULL); + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "soc/exynos-pmu:online", + NULL, gs101_cpuhp_pmu_offline); + } + } + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init) pmu_context->pmu_data->pmu_init(); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 0a49a2c9a08e..0938bb4fe15f 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -22,6 +22,7 @@ struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; const struct exynos_pmu_conf *pmu_config_extra; bool pmu_secure; + bool pmu_cpuhp; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c index 114352695ac2..5f7bdf3bab05 100644 --- a/drivers/soc/samsung/exynos-usi.c +++ b/drivers/soc/samsung/exynos-usi.c @@ -6,6 +6,7 @@ * Samsung Exynos USI driver (Universal Serial Interface). */ +#include <linux/array_size.h> #include <linux/clk.h> #include <linux/mfd/syscon.h> #include <linux/module.h> @@ -16,6 +17,18 @@ #include <dt-bindings/soc/samsung,exynos-usi.h> +/* USIv1: System Register: SW_CONF register bits */ +#define USI_V1_SW_CONF_NONE 0x0 +#define USI_V1_SW_CONF_I2C0 0x1 +#define USI_V1_SW_CONF_I2C1 0x2 +#define USI_V1_SW_CONF_I2C0_1 0x3 +#define USI_V1_SW_CONF_SPI 0x4 +#define USI_V1_SW_CONF_UART 0x8 +#define USI_V1_SW_CONF_UART_I2C1 0xa +#define USI_V1_SW_CONF_MASK (USI_V1_SW_CONF_I2C0 | USI_V1_SW_CONF_I2C1 | \ + USI_V1_SW_CONF_I2C0_1 | USI_V1_SW_CONF_SPI | \ + USI_V1_SW_CONF_UART | USI_V1_SW_CONF_UART_I2C1) + /* USIv2: System Register: SW_CONF register bits */ #define USI_V2_SW_CONF_NONE 0x0 #define USI_V2_SW_CONF_UART BIT(0) @@ -34,7 +47,8 @@ #define USI_OPTION_CLKSTOP_ON BIT(2) enum exynos_usi_ver { - USI_VER2 = 2, + USI_VER1 = 0, + USI_VER2, }; struct exynos_usi_variant { @@ -66,19 +80,39 @@ struct exynos_usi_mode { unsigned int val; /* mode register value */ }; -static const struct exynos_usi_mode exynos_usi_modes[] = { - [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, - [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, - [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, - [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, +#define USI_MODES_MAX (USI_MODE_UART_I2C1 + 1) +static const struct exynos_usi_mode exynos_usi_modes[][USI_MODES_MAX] = { + [USI_VER1] = { + [USI_MODE_NONE] = { .name = "none", .val = USI_V1_SW_CONF_NONE }, + [USI_MODE_UART] = { .name = "uart", .val = USI_V1_SW_CONF_UART }, + [USI_MODE_SPI] = { .name = "spi", .val = USI_V1_SW_CONF_SPI }, + [USI_MODE_I2C] = { .name = "i2c", .val = USI_V1_SW_CONF_I2C0 }, + [USI_MODE_I2C1] = { .name = "i2c1", .val = USI_V1_SW_CONF_I2C1 }, + [USI_MODE_I2C0_1] = { .name = "i2c0_1", .val = USI_V1_SW_CONF_I2C0_1 }, + [USI_MODE_UART_I2C1] = { .name = "uart_i2c1", .val = USI_V1_SW_CONF_UART_I2C1 }, + }, [USI_VER2] = { + [USI_MODE_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, + [USI_MODE_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, + [USI_MODE_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, + [USI_MODE_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, + }, }; static const char * const exynos850_usi_clk_names[] = { "pclk", "ipclk" }; static const struct exynos_usi_variant exynos850_usi_data = { .ver = USI_VER2, .sw_conf_mask = USI_V2_SW_CONF_MASK, - .min_mode = USI_V2_NONE, - .max_mode = USI_V2_I2C, + .min_mode = USI_MODE_NONE, + .max_mode = USI_MODE_I2C, + .num_clks = ARRAY_SIZE(exynos850_usi_clk_names), + .clk_names = exynos850_usi_clk_names, +}; + +static const struct exynos_usi_variant exynos8895_usi_data = { + .ver = USI_VER1, + .sw_conf_mask = USI_V1_SW_CONF_MASK, + .min_mode = USI_MODE_NONE, + .max_mode = USI_MODE_UART_I2C1, .num_clks = ARRAY_SIZE(exynos850_usi_clk_names), .clk_names = exynos850_usi_clk_names, }; @@ -87,6 +121,9 @@ static const struct of_device_id exynos_usi_dt_match[] = { { .compatible = "samsung,exynos850-usi", .data = &exynos850_usi_data, + }, { + .compatible = "samsung,exynos8895-usi", + .data = &exynos8895_usi_data, }, { } /* sentinel */ }; @@ -109,14 +146,15 @@ static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) if (mode < usi->data->min_mode || mode > usi->data->max_mode) return -EINVAL; - val = exynos_usi_modes[mode].val; + val = exynos_usi_modes[usi->data->ver][mode].val; ret = regmap_update_bits(usi->sysreg, usi->sw_conf, usi->data->sw_conf_mask, val); if (ret) return ret; usi->mode = mode; - dev_dbg(usi->dev, "protocol: %s\n", exynos_usi_modes[usi->mode].name); + dev_dbg(usi->dev, "protocol: %s\n", + exynos_usi_modes[usi->data->ver][usi->mode].name); return 0; } @@ -168,10 +206,42 @@ static int exynos_usi_configure(struct exynos_usi *usi) if (ret) return ret; - if (usi->data->ver == USI_VER2) - return exynos_usi_enable(usi); + if (usi->data->ver == USI_VER1) + ret = clk_bulk_prepare_enable(usi->data->num_clks, + usi->clks); + else if (usi->data->ver == USI_VER2) + ret = exynos_usi_enable(usi); - return 0; + return ret; +} + +static void exynos_usi_unconfigure(void *data) +{ + struct exynos_usi *usi = data; + u32 val; + int ret; + + if (usi->data->ver == USI_VER1) { + clk_bulk_disable_unprepare(usi->data->num_clks, usi->clks); + return; + } + + ret = clk_bulk_prepare_enable(usi->data->num_clks, usi->clks); + if (ret) + return; + + /* Make sure that we've stopped providing the clock to USI IP */ + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKREQ_ON; + val |= USI_OPTION_CLKSTOP_ON; + writel(val, usi->regs + USI_OPTION); + + /* Set USI block state to reset */ + val = readl(usi->regs + USI_CON); + val |= USI_CON_RESET; + writel(val, usi->regs + USI_CON); + + clk_bulk_disable_unprepare(usi->data->num_clks, usi->clks); } static int exynos_usi_parse_dt(struct device_node *np, struct exynos_usi *usi) @@ -186,15 +256,11 @@ static int exynos_usi_parse_dt(struct device_node *np, struct exynos_usi *usi) return -EINVAL; usi->mode = mode; - usi->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); + usi->sysreg = syscon_regmap_lookup_by_phandle_args(np, "samsung,sysreg", + 1, &usi->sw_conf); if (IS_ERR(usi->sysreg)) return PTR_ERR(usi->sysreg); - ret = of_property_read_u32_index(np, "samsung,sysreg", 1, - &usi->sw_conf); - if (ret) - return ret; - usi->clkreq_on = of_property_read_bool(np, "samsung,clkreq-on"); return 0; @@ -255,6 +321,10 @@ static int exynos_usi_probe(struct platform_device *pdev) if (ret) return ret; + ret = devm_add_action_or_reset(&pdev->dev, exynos_usi_unconfigure, usi); + if (ret) + return ret; + /* Make it possible to embed protocol nodes into USI np */ return of_platform_populate(np, NULL, NULL, dev); } diff --git a/drivers/soc/samsung/exynos3250-pmu.c b/drivers/soc/samsung/exynos3250-pmu.c index 30f230ed1769..4bad12a99542 100644 --- a/drivers/soc/samsung/exynos3250-pmu.c +++ b/drivers/soc/samsung/exynos3250-pmu.c @@ -5,6 +5,7 @@ // // Exynos3250 - CPU PMU (Power Management Unit) support +#include <linux/array_size.h> #include <linux/soc/samsung/exynos-regs-pmu.h> #include <linux/soc/samsung/exynos-pmu.h> diff --git a/drivers/soc/samsung/exynos5250-pmu.c b/drivers/soc/samsung/exynos5250-pmu.c index 7a2d50be6b4a..2ae5c3e1b07a 100644 --- a/drivers/soc/samsung/exynos5250-pmu.c +++ b/drivers/soc/samsung/exynos5250-pmu.c @@ -5,6 +5,7 @@ // // Exynos5250 - CPU PMU (Power Management Unit) support +#include <linux/array_size.h> #include <linux/soc/samsung/exynos-regs-pmu.h> #include <linux/soc/samsung/exynos-pmu.h> diff --git a/drivers/soc/samsung/exynos5420-pmu.c b/drivers/soc/samsung/exynos5420-pmu.c index 6fedcd78cb45..58a2209795f7 100644 --- a/drivers/soc/samsung/exynos5420-pmu.c +++ b/drivers/soc/samsung/exynos5420-pmu.c @@ -5,6 +5,7 @@ // // Exynos5420 - CPU PMU (Power Management Unit) support +#include <linux/array_size.h> #include <linux/pm.h> #include <linux/soc/samsung/exynos-regs-pmu.h> #include <linux/soc/samsung/exynos-pmu.h> diff --git a/drivers/soc/sophgo/Kconfig b/drivers/soc/sophgo/Kconfig new file mode 100644 index 000000000000..45f78b270c91 --- /dev/null +++ b/drivers/soc/sophgo/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Sophgo SoC drivers +# + +if ARCH_SOPHGO || COMPILE_TEST +menu "Sophgo SoC drivers" + +config SOPHGO_CV1800_RTCSYS + tristate "Sophgo CV1800 RTC MFD" + select MFD_CORE + help + If you say yes here you get support the RTC MFD driver for Sophgo + CV1800 series SoC. The RTC module comprises a 32kHz oscillator, + Power-on-Reset (PoR) sub-module, HW state machine to control chip + power-on, power-off and reset. Furthermore, the 8051 subsystem is + located within RTCSYS including associated SRAM block. + + This driver can also be built as a module. If so, the module will be + called cv1800-rtcsys. + +config SOPHGO_SG2044_TOPSYS + tristate "Sophgo SG2044 TOP syscon driver" + select MFD_CORE + help + This is the core driver for the Sophgo SG2044 TOP system + controller device. This driver provide PLL clock device + for the SoC. + + This driver can also be built as a module. If so, the module + will be called sg2044-topsys. + +endmenu +endif diff --git a/drivers/soc/sophgo/Makefile b/drivers/soc/sophgo/Makefile new file mode 100644 index 000000000000..27f68df22c4d --- /dev/null +++ b/drivers/soc/sophgo/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_SOPHGO_CV1800_RTCSYS) += cv1800-rtcsys.o +obj-$(CONFIG_SOPHGO_SG2044_TOPSYS) += sg2044-topsys.o diff --git a/drivers/soc/sophgo/cv1800-rtcsys.c b/drivers/soc/sophgo/cv1800-rtcsys.c new file mode 100644 index 000000000000..fdae2e2a61c5 --- /dev/null +++ b/drivers/soc/sophgo/cv1800-rtcsys.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Sophgo CV1800 series SoC RTC subsystem + * + * The RTC module comprises a 32kHz oscillator, Power-on-Reset (PoR) sub-module, + * HW state machine to control chip power-on, power-off and reset. Furthermore, + * the 8051 subsystem is located within RTCSYS including associated SRAM block. + * + * Copyright (C) 2025 Alexander Sverdlin <alexander.sverdlin@gmail.com> + * + */ + +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/property.h> + +static struct resource cv1800_rtcsys_irq_resources[] = { + DEFINE_RES_IRQ_NAMED(0, "alarm"), +}; + +static const struct mfd_cell cv1800_rtcsys_subdev[] = { + { + .name = "cv1800b-rtc", + .num_resources = 1, + .resources = &cv1800_rtcsys_irq_resources[0], + }, +}; + +static int cv1800_rtcsys_probe(struct platform_device *pdev) +{ + int irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return irq; + cv1800_rtcsys_irq_resources[0].start = irq; + cv1800_rtcsys_irq_resources[0].end = irq; + + return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, + cv1800_rtcsys_subdev, + ARRAY_SIZE(cv1800_rtcsys_subdev), + NULL, 0, NULL); +} + +static const struct of_device_id cv1800_rtcsys_of_match[] = { + { .compatible = "sophgo,cv1800b-rtc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, cv1800_rtcsys_of_match); + +static struct platform_driver cv1800_rtcsys_mfd = { + .probe = cv1800_rtcsys_probe, + .driver = { + .name = "cv1800_rtcsys", + .of_match_table = cv1800_rtcsys_of_match, + }, +}; +module_platform_driver(cv1800_rtcsys_mfd); + +MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>"); +MODULE_DESCRIPTION("Sophgo CV1800 series SoC RTC subsystem driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/sophgo/sg2044-topsys.c b/drivers/soc/sophgo/sg2044-topsys.c new file mode 100644 index 000000000000..179f2620b2a9 --- /dev/null +++ b/drivers/soc/sophgo/sg2044-topsys.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2044 multi-function system controller driver + * + * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> + */ + +#include <linux/mfd/core.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/resource.h> + +static const struct mfd_cell sg2044_topsys_subdev[] = { + { + .name = "sg2044-pll", + }, +}; + +static int sg2044_topsys_probe(struct platform_device *pdev) +{ + return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, + sg2044_topsys_subdev, + ARRAY_SIZE(sg2044_topsys_subdev), + NULL, 0, NULL); +} + +static const struct of_device_id sg2044_topsys_of_match[] = { + { .compatible = "sophgo,sg2044-top-syscon" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sg2044_topsys_of_match); + +static struct platform_driver sg2044_topsys_driver = { + .probe = sg2044_topsys_probe, + .driver = { + .name = "sg2044-topsys", + .of_match_table = sg2044_topsys_of_match, + }, +}; +module_platform_driver(sg2044_topsys_driver); + +MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>"); +MODULE_DESCRIPTION("Sophgo SG2044 multi-function system controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a08c377933c5..e0d67bfe955c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -47,6 +47,7 @@ #include <linux/seq_file.h> #include <linux/slab.h> #include <linux/spinlock.h> +#include <linux/string_choices.h> #include <linux/syscore_ops.h> #include <soc/tegra/common.h> @@ -1181,7 +1182,7 @@ static int powergate_show(struct seq_file *s, void *data) continue; seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], - status ? "yes" : "no"); + str_yes_no(status)); } return 0; @@ -2499,8 +2500,9 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) pmc->irq.irq_set_type = pmc->soc->irq_set_type; pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; - pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, - &tegra_pmc_irq_domain_ops, pmc); + pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, + of_fwnode_handle(pmc->dev->of_node), + &tegra_pmc_irq_domain_ops, pmc); if (!pmc->domain) { dev_err(pmc->dev, "failed to allocate domain\n"); return -ENOMEM; diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 82a15cad1c6c..7602b8a909b0 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -1291,7 +1291,7 @@ struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np, mutex_lock(&k3_ringacc_list_lock); list_for_each_entry(entry, &k3_ringacc_list, list) - if (entry->dev->of_node == ringacc_np) { + if (device_match_of_node(entry->dev, ringacc_np)) { ringacc = entry; break; } diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index 4fb0f0a24828..d716be113c84 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -43,6 +43,7 @@ #define JTAG_ID_PARTNO_AM62AX 0xBB8D #define JTAG_ID_PARTNO_AM62PX 0xBB9D #define JTAG_ID_PARTNO_J722S 0xBBA0 +#define JTAG_ID_PARTNO_AM62LX 0xBBA7 static const struct k3_soc_id { unsigned int id; @@ -58,6 +59,7 @@ static const struct k3_soc_id { { JTAG_ID_PARTNO_AM62AX, "AM62AX" }, { JTAG_ID_PARTNO_AM62PX, "AM62PX" }, { JTAG_ID_PARTNO_J722S, "J722S" }, + { JTAG_ID_PARTNO_AM62LX, "AM62LX" }, }; static const char * const j721e_rev_string_map[] = { @@ -105,6 +107,12 @@ err_unknown_variant: return -ENODEV; } +static const struct regmap_config k3_chipinfo_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int k3_chipinfo_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -112,13 +120,18 @@ static int k3_chipinfo_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct soc_device *soc_dev; struct regmap *regmap; + void __iomem *base; u32 partno_id; u32 variant; u32 jtag_id; u32 mfg; int ret; - regmap = device_node_to_regmap(node); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = regmap_init_mmio(dev, base, &k3_chipinfo_regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index ea52425864a9..6e56e7609ccd 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -252,8 +252,7 @@ static struct knav_queue *__knav_queue_open(struct knav_queue_inst *inst, return qh; err: - if (qh->stats) - free_percpu(qh->stats); + free_percpu(qh->stats); devm_kfree(inst->kdev->dev, qh); return ERR_PTR(ret); } diff --git a/drivers/soc/ti/ti_sci_inta_msi.c b/drivers/soc/ti/ti_sci_inta_msi.c index c36364522157..193266f5e3f9 100644 --- a/drivers/soc/ti/ti_sci_inta_msi.c +++ b/drivers/soc/ti/ti_sci_inta_msi.c @@ -103,19 +103,15 @@ int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev, if (ret) return ret; - msi_lock_descs(dev); + guard(msi_descs_lock)(dev); nvec = ti_sci_inta_msi_alloc_descs(dev, res); - if (nvec <= 0) { - ret = nvec; - goto unlock; - } + if (nvec <= 0) + return nvec; /* Use alloc ALL as it's unclear whether there are gaps in the indices */ ret = msi_domain_alloc_irqs_all_locked(dev, MSI_DEFAULT_DOMAIN, nvec); if (ret) dev_err(dev, "Failed to allocate IRQs %d\n", ret); -unlock: - msi_unlock_descs(dev); return ret; } EXPORT_SYMBOL_GPL(ti_sci_inta_msi_domain_alloc_irqs); diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 79dde9a7ec63..5845fc652adc 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -644,11 +644,9 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0); - if (IS_ERR(m3_ipc->mbox)) { - dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n", - PTR_ERR(m3_ipc->mbox)); - return PTR_ERR(m3_ipc->mbox); - } + if (IS_ERR(m3_ipc->mbox)) + return dev_err_probe(dev, PTR_ERR(m3_ipc->mbox), + "IPC Request for A8->M3 Channel failed!\n"); if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) { dev_err(&pdev->dev, "could not get rproc phandle\n"); diff --git a/drivers/soc/vt8500/Kconfig b/drivers/soc/vt8500/Kconfig new file mode 100644 index 000000000000..b4cc0ba1128b --- /dev/null +++ b/drivers/soc/vt8500/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_VT8500 || COMPILE_TEST + +menu "VIA/WonderMedia SoC drivers" + +config WMT_SOCINFO + bool "VIA/WonderMedia SoC Information driver" + default ARCH_VT8500 + select SOC_BUS + help + Say yes to support decoding of VIA/WonderMedia system configuration + register information. This currently includes just the chip ID register + which helps identify the exact hardware revision of the SoC the kernel + is running on (to know if any revision-specific quirks are required) + +endmenu + +endif diff --git a/drivers/soc/vt8500/Makefile b/drivers/soc/vt8500/Makefile new file mode 100644 index 000000000000..05964c5f2890 --- /dev/null +++ b/drivers/soc/vt8500/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_WMT_SOCINFO) += wmt-socinfo.o diff --git a/drivers/soc/vt8500/wmt-socinfo.c b/drivers/soc/vt8500/wmt-socinfo.c new file mode 100644 index 000000000000..461f8c1ae56e --- /dev/null +++ b/drivers/soc/vt8500/wmt-socinfo.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2025 Alexey Charkov <alchark@gmail.com> + * Based on aspeed-socinfo.c + */ + +#include <linux/dev_printk.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/sys_soc.h> + +static const struct { + const char *name; + const u32 id; +} chip_id_table[] = { + /* VIA */ + { "VT8420", 0x3300 }, + { "VT8430", 0x3357 }, + { "VT8500", 0x3400 }, + + /* WonderMedia */ + { "WM8425", 0x3429 }, + { "WM8435", 0x3437 }, + { "WM8440", 0x3451 }, + { "WM8505", 0x3426 }, + { "WM8650", 0x3465 }, + { "WM8750", 0x3445 }, + { "WM8850", 0x3481 }, + { "WM8880", 0x3498 }, +}; + +static const char *sccid_to_name(u32 sccid) +{ + u32 id = sccid >> 16; + unsigned int i; + + for (i = 0 ; i < ARRAY_SIZE(chip_id_table) ; ++i) { + if (chip_id_table[i].id == id) + return chip_id_table[i].name; + } + + return "Unknown"; +} + +static int wmt_socinfo_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct soc_device_attribute *attrs; + struct soc_device *soc_dev; + char letter, digit; + void __iomem *reg; + u32 sccid; + + reg = devm_of_iomap(&pdev->dev, np, 0, NULL); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + sccid = readl(reg); + + attrs = devm_kzalloc(&pdev->dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + /* + * Machine: VIA APC Rock + * Family: WM8850 + * Revision: A2 + * SoC ID: raw silicon revision id (34810103 in hexadecimal) + */ + + attrs->family = sccid_to_name(sccid); + + letter = (sccid >> 8) & 0xf; + letter = (letter - 1) + 'A'; + digit = sccid & 0xff; + digit = (digit - 1) + '0'; + attrs->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%c%c", letter, digit); + + attrs->soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%08x", sccid); + + if (!attrs->revision || !attrs->soc_id) + return -ENOMEM; + + soc_dev = soc_device_register(attrs); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + dev_info(&pdev->dev, + "VIA/WonderMedia %s rev %s (%s)\n", + attrs->family, + attrs->revision, + attrs->soc_id); + + platform_set_drvdata(pdev, soc_dev); + return 0; +} + +static void wmt_socinfo_remove(struct platform_device *pdev) +{ + struct soc_device *soc_dev = platform_get_drvdata(pdev); + + soc_device_unregister(soc_dev); +} + +static const struct of_device_id wmt_socinfo_ids[] = { + { .compatible = "via,vt8500-scc-id" }, + { /* Sentinel */ }, +}; + +static struct platform_driver wmt_socinfo = { + .probe = wmt_socinfo_probe, + .remove = wmt_socinfo_remove, + .driver = { + .name = "wmt-socinfo", + .of_match_table = wmt_socinfo_ids, + }, +}; +module_platform_driver(wmt_socinfo); + +MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>"); +MODULE_DESCRIPTION("VIA/WonderMedia socinfo driver"); +MODULE_LICENSE("GPL"); |