diff options
Diffstat (limited to 'drivers/pinctrl/sophgo')
| -rw-r--r-- | drivers/pinctrl/sophgo/Kconfig | 46 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/Makefile | 8 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-cv1800b.c | 27 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-cv1812h.c | 27 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-cv18xx.c | 602 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-cv18xx.h | 66 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2000.c | 27 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2002.c | 27 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c | 296 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2042.c | 655 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2042.h | 49 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sg2044.c | 718 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sophgo-common.c | 451 | ||||
| -rw-r--r-- | drivers/pinctrl/sophgo/pinctrl-sophgo.h | 136 |
14 files changed, 2593 insertions, 542 deletions
diff --git a/drivers/pinctrl/sophgo/Kconfig b/drivers/pinctrl/sophgo/Kconfig index c05f909a8838..9b0a3a4753b1 100644 --- a/drivers/pinctrl/sophgo/Kconfig +++ b/drivers/pinctrl/sophgo/Kconfig @@ -3,17 +3,21 @@ # Sophgo SoC PINCTRL drivers # -config PINCTRL_SOPHGO_CV18XX - bool +config PINCTRL_SOPHGO_COMMON + tristate select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF +config PINCTRL_SOPHGO_CV18XX_OPS + bool + config PINCTRL_SOPHGO_CV1800B tristate "Sophgo CV1800B SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for CV1800B SoC. This pin controller allows selecting the mux function for @@ -24,7 +28,8 @@ config PINCTRL_SOPHGO_CV1812H tristate "Sophgo CV1812H SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for CV1812H SoC. This pin controller allows selecting the mux function for @@ -35,7 +40,8 @@ config PINCTRL_SOPHGO_SG2000 tristate "Sophgo SG2000 SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for SG2000 SoC. This pin controller allows selecting the mux function for @@ -46,9 +52,37 @@ config PINCTRL_SOPHGO_SG2002 tristate "Sophgo SG2002 SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for SG2002 SoC. This pin controller allows selecting the mux function for each pin. This driver can also be built as a module called pinctrl-sg2002. + +config PINCTRL_SOPHGO_SG2042_OPS + bool + +config PINCTRL_SOPHGO_SG2042 + tristate "Sophgo SG2042 SoC Pinctrl driver" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_SG2042_OPS + help + Say Y to select the pinctrl driver for SG2042 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-sg2042. + +config PINCTRL_SOPHGO_SG2044 + tristate "Sophgo SG2044 SoC Pinctrl driver" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_SG2042_OPS + help + Say Y to select the pinctrl driver for SG2044 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-sg2044. diff --git a/drivers/pinctrl/sophgo/Makefile b/drivers/pinctrl/sophgo/Makefile index 4113a5c9191b..479c65e6dbc0 100644 --- a/drivers/pinctrl/sophgo/Makefile +++ b/drivers/pinctrl/sophgo/Makefile @@ -1,7 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_SOPHGO_CV18XX) += pinctrl-cv18xx.o +obj-$(CONFIG_PINCTRL_SOPHGO_COMMON) += pinctrl-sophgo.o +pinctrl-sophgo-objs += pinctrl-sophgo-common.o +pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_CV18XX_OPS) += pinctrl-cv18xx.o +pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_SG2042_OPS) += pinctrl-sg2042-ops.o + obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o +obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o +obj-$(CONFIG_PINCTRL_SOPHGO_SG2044) += pinctrl-sg2044.o diff --git a/drivers/pinctrl/sophgo/pinctrl-cv1800b.c b/drivers/pinctrl/sophgo/pinctrl-cv1800b.c index 3322906689e7..82db60212477 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv1800b.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv1800b.c @@ -34,8 +34,9 @@ static const char *const cv1800b_power_domain_desc[] = { [VDDIO_SD0_SPI] = "VDDIO_SD0_SPI", }; -static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int cv1800b_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -54,8 +55,9 @@ static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int cv1800b_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int cv1800b_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -108,9 +110,10 @@ static const u32 cv1800b_eth_oc_map[] = { 17800 }; -static int cv1800b_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1800b_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -153,9 +156,10 @@ static const u32 cv1800b_18od33_3v3_schmitt_map[] = { 1100000 }; -static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1800b_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -177,11 +181,11 @@ static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops cv1800b_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops cv1800b_vddio_cfg_ops = { .get_pull_up = cv1800b_get_pull_up, .get_pull_down = cv1800b_get_pull_down, .get_oc_map = cv1800b_get_oc_map, - .get_schmitt_map = cv1800b_get_schmitt_map, + .get_schmitt_map = cv1800b_get_schmitt_map, }; static const struct pinctrl_pin_desc cv1800b_pins[] = { @@ -433,13 +437,18 @@ static const struct cv1800_pin cv1800b_pin_data[ARRAY_SIZE(cv1800b_pins)] = { CV1800_PINCONF_AREA_SYS, 0x120, 5), }; -static const struct cv1800_pinctrl_data cv1800b_pindata = { +static const struct sophgo_pinctrl_data cv1800b_pindata = { .pins = cv1800b_pins, .pindata = cv1800b_pin_data, .pdnames = cv1800b_power_domain_desc, .vddio_ops = &cv1800b_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(cv1800b_pins), - .npd = ARRAY_SIZE(cv1800b_power_domain_desc), + .npds = ARRAY_SIZE(cv1800b_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id cv1800b_pinctrl_ids[] = { @@ -449,7 +458,7 @@ static const struct of_device_id cv1800b_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids); static struct platform_driver cv1800b_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "cv1800b-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-cv1812h.c b/drivers/pinctrl/sophgo/pinctrl-cv1812h.c index 5632290b46fa..881a4d7ef589 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv1812h.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv1812h.c @@ -40,8 +40,9 @@ static const char *const cv1812h_power_domain_desc[] = { [VDDIO_VIVO] = "VDDIO_VIVO", }; -static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int cv1812h_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -60,8 +61,9 @@ static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int cv1812h_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int cv1812h_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -114,9 +116,10 @@ static const u32 cv1812h_eth_oc_map[] = { 17800 }; -static int cv1812h_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1812h_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -159,9 +162,10 @@ static const u32 cv1812h_18od33_3v3_schmitt_map[] = { 1100000 }; -static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1812h_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -183,11 +187,11 @@ static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops cv1812h_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops cv1812h_vddio_cfg_ops = { .get_pull_up = cv1812h_get_pull_up, .get_pull_down = cv1812h_get_pull_down, .get_oc_map = cv1812h_get_oc_map, - .get_schmitt_map = cv1812h_get_schmitt_map, + .get_schmitt_map = cv1812h_get_schmitt_map, }; static const struct pinctrl_pin_desc cv1812h_pins[] = { @@ -742,13 +746,18 @@ static const struct cv1800_pin cv1812h_pin_data[ARRAY_SIZE(cv1812h_pins)] = { CV1800_PINCONF_AREA_RTC, 0x028), }; -static const struct cv1800_pinctrl_data cv1812h_pindata = { +static const struct sophgo_pinctrl_data cv1812h_pindata = { .pins = cv1812h_pins, .pindata = cv1812h_pin_data, .pdnames = cv1812h_power_domain_desc, .vddio_ops = &cv1812h_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(cv1812h_pins), - .npd = ARRAY_SIZE(cv1812h_power_domain_desc), + .npds = ARRAY_SIZE(cv1812h_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id cv1812h_pinctrl_ids[] = { @@ -758,7 +767,7 @@ static const struct of_device_id cv1812h_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, cv1812h_pinctrl_ids); static struct platform_driver cv1812h_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "cv1812h-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c index 57f2674e75d6..c3a2dcf71f2a 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c @@ -15,8 +15,6 @@ #include <linux/seq_file.h> #include <linux/spinlock.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -24,35 +22,15 @@ #include <dt-bindings/pinctrl/pinctrl-cv18xx.h> -#include "../core.h" #include "../pinctrl-utils.h" -#include "../pinconf.h" #include "../pinmux.h" #include "pinctrl-cv18xx.h" -struct cv1800_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl_dev; - const struct cv1800_pinctrl_data *data; - struct pinctrl_desc pdesc; +struct cv1800_priv { u32 *power_cfg; - - struct mutex mutex; - raw_spinlock_t lock; - void __iomem *regs[2]; }; -struct cv1800_pin_mux_config { - struct cv1800_pin *pin; - u32 config; -}; - -static unsigned int cv1800_dt_get_pin(u32 value) -{ - return value & GENMASK(15, 0); -} - static unsigned int cv1800_dt_get_pin_mux(u32 value) { return (value >> 16) & GENMASK(7, 0); @@ -66,40 +44,28 @@ static unsigned int cv1800_dt_get_pin_mux2(u32 value) #define cv1800_pinctrl_get_component_addr(pctrl, _comp) \ ((pctrl)->regs[(_comp)->area] + (_comp)->offset) -static int cv1800_cmp_pin(const void *key, const void *pivot) -{ - const struct cv1800_pin *pin = pivot; - int pin_id = (long)key; - int pivid = pin->pin; - - return pin_id - pivid; -} - -static int cv1800_set_power_cfg(struct cv1800_pinctrl *pctrl, +static int cv1800_set_power_cfg(struct sophgo_pinctrl *pctrl, u8 domain, u32 cfg) { - if (domain >= pctrl->data->npd) + struct cv1800_priv *priv = pctrl->priv_ctrl; + + if (domain >= pctrl->data->npds) return -ENOTSUPP; - if (pctrl->power_cfg[domain] && pctrl->power_cfg[domain] != cfg) + if (priv->power_cfg[domain] && priv->power_cfg[domain] != cfg) return -EINVAL; - pctrl->power_cfg[domain] = cfg; + priv->power_cfg[domain] = cfg; return 0; } -static int cv1800_get_power_cfg(struct cv1800_pinctrl *pctrl, +static int cv1800_get_power_cfg(struct sophgo_pinctrl *pctrl, u8 domain) { - return pctrl->power_cfg[domain]; -} + struct cv1800_priv *priv = pctrl->priv_ctrl; -static struct cv1800_pin *cv1800_get_pin(struct cv1800_pinctrl *pctrl, - unsigned long pin) -{ - return bsearch((void *)pin, pctrl->data->pindata, pctrl->data->npins, - sizeof(struct cv1800_pin), cv1800_cmp_pin); + return priv->power_cfg[domain]; } #define PIN_BGA_ID_OFFSET 8 @@ -112,7 +78,7 @@ static const char *const io_type_desc[] = { "ETH" }; -static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl, +static const char *cv1800_get_power_cfg_desc(struct sophgo_pinctrl *pctrl, u8 domain) { return pctrl->data->pdnames[domain]; @@ -121,53 +87,57 @@ static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl, static void cv1800_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *seq, unsigned int pin_id) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct cv1800_priv *priv = pctrl->priv_ctrl; + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); + u32 pin_hwid = pin->pin.id; u32 value; void __iomem *reg; - if (pin->pin >> PIN_BGA_ID_OFFSET) + if (pin_hwid >> PIN_BGA_ID_OFFSET) seq_printf(seq, "pos: %c%u ", - 'A' + (pin->pin >> PIN_BGA_ID_OFFSET) - 1, - pin->pin & PIN_BGA_ID_MASK); + 'A' + (pin_hwid >> PIN_BGA_ID_OFFSET) - 1, + pin_hwid & PIN_BGA_ID_MASK); else - seq_printf(seq, "pos: %u ", pin->pin); + seq_printf(seq, "pos: %u ", pin_hwid); seq_printf(seq, "power-domain: %s ", cv1800_get_power_cfg_desc(pctrl, pin->power_domain)); seq_printf(seq, "type: %s ", io_type_desc[type]); - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux); + reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux); value = readl(reg); seq_printf(seq, "mux: 0x%08x ", value); - if (pin->flags & CV1800_PIN_HAVE_MUX2) { - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2); + if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { + reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux2); value = readl(reg); seq_printf(seq, "mux2: 0x%08x ", value); } if (type == IO_TYPE_1V8_ONLY || type == IO_TYPE_1V8_OR_3V3) { - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf); + reg = cv1800_pinctrl_get_component_addr(priv, &pin->conf); value = readl(reg); seq_printf(seq, "conf: 0x%08x ", value); } } -static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *config) +static int cv1800_verify_pinmux_config(const struct sophgo_pin_mux_config *config) { + struct cv1800_pin *pin = sophgo_to_cv1800_pin(config->pin); unsigned int mux = cv1800_dt_get_pin_mux(config->config); unsigned int mux2 = cv1800_dt_get_pin_mux2(config->config); - if (mux > config->pin->mux.max) + if (mux > pin->mux.max) return -EINVAL; - if (config->pin->flags & CV1800_PIN_HAVE_MUX2) { - if (mux != config->pin->mux2.pfunc) + if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { + if (mux != pin->mux2.pfunc) return -EINVAL; - if (mux2 > config->pin->mux2.max) + if (mux2 > pin->mux2.max) return -EINVAL; } else { if (mux2 != PIN_MUX_INVALD) @@ -177,9 +147,10 @@ static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *confi return 0; } -static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux, - unsigned long npins) +static int cv1800_verify_pin_group(const struct sophgo_pin_mux_config *mux, + unsigned int npins) { + struct cv1800_pin *pin; enum cv1800_pin_io_type type; u8 power_domain; int i; @@ -187,232 +158,78 @@ static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux, if (npins == 1) return 0; - type = cv1800_pin_io_type(mux[0].pin); - power_domain = mux[0].pin->power_domain; + pin = sophgo_to_cv1800_pin(mux[0].pin); + type = cv1800_pin_io_type(pin); + power_domain = pin->power_domain; for (i = 0; i < npins; i++) { - if (type != cv1800_pin_io_type(mux[i].pin) || - power_domain != mux[i].pin->power_domain) + pin = sophgo_to_cv1800_pin(mux[i].pin); + + if (type != cv1800_pin_io_type(pin) || + power_domain != pin->power_domain) return -ENOTSUPP; } return 0; } -static int cv1800_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, - unsigned int *num_maps) +static int cv1800_dt_node_to_map_post(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct device *dev = pctrl->dev; - struct device_node *child; - struct pinctrl_map *map; - const char **grpnames; - const char *grpname; - int ngroups = 0; - int nmaps = 0; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(pinmuxs[0].pin); + u32 power; int ret; - for_each_available_child_of_node(np, child) - ngroups += 1; - - grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); - if (!grpnames) - return -ENOMEM; - - map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - ngroups = 0; - mutex_lock(&pctrl->mutex); - for_each_available_child_of_node(np, child) { - int npins = of_property_count_u32_elems(child, "pinmux"); - unsigned int *pins; - struct cv1800_pin_mux_config *pinmuxs; - u32 config, power; - int i; - - if (npins < 1) { - dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", - np, child); - ret = -EINVAL; - goto dt_failed; - } - - grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", - np, child); - if (!grpname) { - ret = -ENOMEM; - goto dt_failed; - } - - grpnames[ngroups++] = grpname; - - pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); - if (!pins) { - ret = -ENOMEM; - goto dt_failed; - } - - pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); - if (!pinmuxs) { - ret = -ENOMEM; - goto dt_failed; - } - - for (i = 0; i < npins; i++) { - ret = of_property_read_u32_index(child, "pinmux", - i, &config); - if (ret) - goto dt_failed; - - pins[i] = cv1800_dt_get_pin(config); - pinmuxs[i].config = config; - pinmuxs[i].pin = cv1800_get_pin(pctrl, pins[i]); - - if (!pinmuxs[i].pin) { - dev_err(dev, "failed to get pin %d\n", pins[i]); - ret = -ENODEV; - goto dt_failed; - } - - ret = cv1800_verify_pinmux_config(&pinmuxs[i]); - if (ret) { - dev_err(dev, "group %s pin %d is invalid\n", - grpname, i); - goto dt_failed; - } - } - - ret = cv1800_verify_pin_group(pinmuxs, npins); - if (ret) { - dev_err(dev, "group %s is invalid\n", grpname); - goto dt_failed; - } - - ret = of_property_read_u32(child, "power-source", &power); - if (ret) - goto dt_failed; - - if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) { - dev_err(dev, "group %s have unsupported power: %u\n", - grpname, power); - ret = -ENOTSUPP; - goto dt_failed; - } - - ret = cv1800_set_power_cfg(pctrl, pinmuxs[0].pin->power_domain, - power); - if (ret) - goto dt_failed; - - map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; - map[nmaps].data.mux.function = np->name; - map[nmaps].data.mux.group = grpname; - nmaps += 1; - - ret = pinconf_generic_parse_dt_config(child, pctldev, - &map[nmaps].data.configs.configs, - &map[nmaps].data.configs.num_configs); - if (ret) { - dev_err(dev, "failed to parse pin config of group %s: %d\n", - grpname, ret); - goto dt_failed; - } - - ret = pinctrl_generic_add_group(pctldev, grpname, - pins, npins, pinmuxs); - if (ret < 0) { - dev_err(dev, "failed to add group %s: %d\n", grpname, ret); - goto dt_failed; - } - - /* don't create a map if there are no pinconf settings */ - if (map[nmaps].data.configs.num_configs == 0) - continue; - - map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - map[nmaps].data.configs.group_or_pin = grpname; - nmaps += 1; - } - - ret = pinmux_generic_add_function(pctldev, np->name, - grpnames, ngroups, NULL); - if (ret < 0) { - dev_err(dev, "error adding function %s: %d\n", np->name, ret); - goto function_failed; - } - - *maps = map; - *num_maps = nmaps; - mutex_unlock(&pctrl->mutex); + ret = of_property_read_u32(cur, "power-source", &power); + if (ret) + return ret; - return 0; + if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) + return -ENOTSUPP; -dt_failed: - of_node_put(child); -function_failed: - pinctrl_utils_free_map(pctldev, map, nmaps); - mutex_unlock(&pctrl->mutex); - return ret; + return cv1800_set_power_cfg(pctrl, pin->power_domain, power); } -static const struct pinctrl_ops cv1800_pctrl_ops = { +const struct pinctrl_ops cv1800_pctrl_ops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = cv1800_pctrl_dbg_show, - .dt_node_to_map = cv1800_pctrl_dt_node_to_map, + .dt_node_to_map = sophgo_pctrl_dt_node_to_map, .dt_free_map = pinctrl_utils_free_map, }; +EXPORT_SYMBOL_GPL(cv1800_pctrl_ops); -static int cv1800_pmx_set_mux(struct pinctrl_dev *pctldev, - unsigned int fsel, unsigned int gsel) +static void cv1800_set_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct group_desc *group; - const struct cv1800_pin_mux_config *configs; - unsigned int i; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - configs = group->data; - - for (i = 0; i < group->grp.npins; i++) { - const struct cv1800_pin *pin = configs[i].pin; - u32 value = configs[i].config; - void __iomem *reg_mux; - void __iomem *reg_mux2; - unsigned long flags; - u32 mux; - u32 mux2; - - reg_mux = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux); - reg_mux2 = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2); - mux = cv1800_dt_get_pin_mux(value); - mux2 = cv1800_dt_get_pin_mux2(value); - - raw_spin_lock_irqsave(&pctrl->lock, flags); - writel_relaxed(mux, reg_mux); - if (mux2 != PIN_MUX_INVALD) - writel_relaxed(mux2, reg_mux2); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - } - - return 0; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); + struct cv1800_priv *priv = pctrl->priv_ctrl; + void __iomem *reg_mux; + void __iomem *reg_mux2; + u32 mux; + u32 mux2; + + reg_mux = cv1800_pinctrl_get_component_addr(priv, &pin->mux); + reg_mux2 = cv1800_pinctrl_get_component_addr(priv, &pin->mux2); + mux = cv1800_dt_get_pin_mux(config); + mux2 = cv1800_dt_get_pin_mux2(config); + + writel_relaxed(mux, reg_mux); + if (mux2 != PIN_MUX_INVALD) + writel_relaxed(mux2, reg_mux2); } -static const struct pinmux_ops cv1800_pmx_ops = { +const struct pinmux_ops cv1800_pmx_ops = { .get_functions_count = pinmux_generic_get_function_count, .get_function_name = pinmux_generic_get_function_name, .get_function_groups = pinmux_generic_get_function_groups, - .set_mux = cv1800_pmx_set_mux, + .set_mux = sophgo_pmx_set_mux, .strict = true, }; +EXPORT_SYMBOL_GPL(cv1800_pmx_ops); #define PIN_IO_PULLUP BIT(2) #define PIN_IO_PULLDOWN BIT(3) @@ -421,94 +238,14 @@ static const struct pinmux_ops cv1800_pmx_ops = { #define PIN_IO_BUS_HOLD BIT(10) #define PIN_IO_OUT_FAST_SLEW BIT(11) -static u32 cv1800_pull_down_typical_resistor(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin) -{ - return pctrl->data->vddio_ops->get_pull_down(pin, pctrl->power_cfg); -} - -static u32 cv1800_pull_up_typical_resistor(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin) -{ - return pctrl->data->vddio_ops->get_pull_up(pin, pctrl->power_cfg); -} - -static int cv1800_pinctrl_oc2reg(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 target) -{ - const u32 *map; - int i, len; - - len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map); - if (len < 0) - return len; - - for (i = 0; i < len; i++) { - if (map[i] >= target) - return i; - } - - return -EINVAL; -} - -static int cv1800_pinctrl_reg2oc(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 reg) -{ - const u32 *map; - int len; - - len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map); - if (len < 0) - return len; - - if (reg >= len) - return -EINVAL; - - return map[reg]; -} - -static int cv1800_pinctrl_schmitt2reg(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 target) -{ - const u32 *map; - int i, len; - - len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg, - &map); - if (len < 0) - return len; - - for (i = 0; i < len; i++) { - if (map[i] == target) - return i; - } - - return -EINVAL; -} - -static int cv1800_pinctrl_reg2schmitt(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 reg) -{ - const u32 *map; - int len; - - len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg, - &map); - if (len < 0) - return len; - - if (reg >= len) - return -EINVAL; - - return map[reg]; -} - static int cv1800_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, unsigned long *config) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct cv1800_priv *priv = pctrl->priv_ctrl; int param = pinconf_to_config_param(*config); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type; u32 value; u32 arg; @@ -522,28 +259,28 @@ static int cv1800_pconf_get(struct pinctrl_dev *pctldev, if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO) return -ENOTSUPP; - value = readl(cv1800_pinctrl_get_component_addr(pctrl, &pin->conf)); + value = readl(cv1800_pinctrl_get_component_addr(priv, &pin->conf)); switch (param) { case PIN_CONFIG_BIAS_PULL_DOWN: enabled = FIELD_GET(PIN_IO_PULLDOWN, value); - arg = cv1800_pull_down_typical_resistor(pctrl, pin); + arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, priv->power_cfg); break; case PIN_CONFIG_BIAS_PULL_UP: enabled = FIELD_GET(PIN_IO_PULLUP, value); - arg = cv1800_pull_up_typical_resistor(pctrl, pin); + arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, priv->power_cfg); break; case PIN_CONFIG_DRIVE_STRENGTH_UA: enabled = true; arg = FIELD_GET(PIN_IO_DRIVE, value); - ret = cv1800_pinctrl_reg2oc(pctrl, pin, arg); + ret = sophgo_pinctrl_reg2oc(pctrl, sp, priv->power_cfg, arg); if (ret < 0) return ret; arg = ret; break; case PIN_CONFIG_INPUT_SCHMITT_UV: arg = FIELD_GET(PIN_IO_SCHMITT, value); - ret = cv1800_pinctrl_reg2schmitt(pctrl, pin, arg); + ret = sophgo_pinctrl_reg2schmitt(pctrl, sp, priv->power_cfg, arg); if (ret < 0) return ret; arg = ret; @@ -570,14 +307,16 @@ static int cv1800_pconf_get(struct pinctrl_dev *pctldev, return enabled ? 0 : -EINVAL; } -static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, +static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, unsigned long *configs, unsigned int num_configs, - u32 *value) + u32 *value, u32 *mask) { + struct cv1800_priv *priv = pctrl->priv_ctrl; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); int i; - u32 v = 0; + u32 v = 0, m = 0; enum cv1800_pin_io_type type; int ret; @@ -596,24 +335,30 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, case PIN_CONFIG_BIAS_PULL_DOWN: v &= ~PIN_IO_PULLDOWN; v |= FIELD_PREP(PIN_IO_PULLDOWN, arg); + m |= PIN_IO_PULLDOWN; break; case PIN_CONFIG_BIAS_PULL_UP: v &= ~PIN_IO_PULLUP; v |= FIELD_PREP(PIN_IO_PULLUP, arg); + m |= PIN_IO_PULLUP; break; case PIN_CONFIG_DRIVE_STRENGTH_UA: - ret = cv1800_pinctrl_oc2reg(pctrl, pin, arg); + ret = sophgo_pinctrl_oc2reg(pctrl, sp, + priv->power_cfg, arg); if (ret < 0) return ret; v &= ~PIN_IO_DRIVE; v |= FIELD_PREP(PIN_IO_DRIVE, ret); + m |= PIN_IO_DRIVE; break; case PIN_CONFIG_INPUT_SCHMITT_UV: - ret = cv1800_pinctrl_schmitt2reg(pctrl, pin, arg); + ret = sophgo_pinctrl_schmitt2reg(pctrl, sp, + priv->power_cfg, arg); if (ret < 0) return ret; v &= ~PIN_IO_SCHMITT; v |= FIELD_PREP(PIN_IO_SCHMITT, ret); + m |= PIN_IO_SCHMITT; break; case PIN_CONFIG_POWER_SOURCE: /* Ignore power source as it is always fixed */ @@ -621,10 +366,12 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, case PIN_CONFIG_SLEW_RATE: v &= ~PIN_IO_OUT_FAST_SLEW; v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg); + m |= PIN_IO_OUT_FAST_SLEW; break; case PIN_CONFIG_BIAS_BUS_HOLD: v &= ~PIN_IO_BUS_HOLD; v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg); + m |= PIN_IO_BUS_HOLD; break; default: return -ENOTSUPP; @@ -632,134 +379,73 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, } *value = v; + *mask = m; return 0; } -static int cv1800_pin_set_config(struct cv1800_pinctrl *pctrl, - unsigned int pin_id, - u32 value) +static int cv1800_set_pinconf_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask) { - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); - unsigned long flags; + struct cv1800_priv *priv = pctrl->priv_ctrl; + struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); void __iomem *addr; + u32 reg; - if (!pin) - return -EINVAL; - - addr = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf); + addr = cv1800_pinctrl_get_component_addr(priv, &pin->conf); - raw_spin_lock_irqsave(&pctrl->lock, flags); - writel(value, addr); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); + reg = readl(addr); + reg &= ~mask; + reg |= value; + writel(reg, addr); return 0; } -static int cv1800_pconf_set(struct pinctrl_dev *pctldev, - unsigned int pin_id, unsigned long *configs, - unsigned int num_configs) -{ - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); - u32 value; - - if (!pin) - return -ENODEV; - - if (cv1800_pinconf_compute_config(pctrl, pin, - configs, num_configs, &value)) - return -ENOTSUPP; - - return cv1800_pin_set_config(pctrl, pin_id, value); -} - -static int cv1800_pconf_group_set(struct pinctrl_dev *pctldev, - unsigned int gsel, - unsigned long *configs, - unsigned int num_configs) -{ - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct group_desc *group; - const struct cv1800_pin_mux_config *pinmuxs; - u32 value; - int i; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - pinmuxs = group->data; - - if (cv1800_pinconf_compute_config(pctrl, pinmuxs[0].pin, - configs, num_configs, &value)) - return -ENOTSUPP; - - for (i = 0; i < group->grp.npins; i++) - cv1800_pin_set_config(pctrl, group->grp.pins[i], value); - - return 0; -} - -static const struct pinconf_ops cv1800_pconf_ops = { +const struct pinconf_ops cv1800_pconf_ops = { .pin_config_get = cv1800_pconf_get, - .pin_config_set = cv1800_pconf_set, - .pin_config_group_set = cv1800_pconf_group_set, + .pin_config_set = sophgo_pconf_set, + .pin_config_group_set = sophgo_pconf_group_set, .is_generic = true, }; +EXPORT_SYMBOL_GPL(cv1800_pconf_ops); -int cv1800_pinctrl_probe(struct platform_device *pdev) +static int cv1800_pinctrl_init(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl) { - struct device *dev = &pdev->dev; - struct cv1800_pinctrl *pctrl; - const struct cv1800_pinctrl_data *pctrl_data; - int ret; - - pctrl_data = device_get_match_data(dev); - if (!pctrl_data) - return -ENODEV; + const struct sophgo_pinctrl_data *pctrl_data = pctrl->data; + struct cv1800_priv *priv; - if (pctrl_data->npins == 0 || pctrl_data->npd == 0) - return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); - - pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); - if (!pctrl) + priv = devm_kzalloc(&pdev->dev, sizeof(struct cv1800_priv), GFP_KERNEL); + if (!priv) return -ENOMEM; - pctrl->power_cfg = devm_kcalloc(dev, pctrl_data->npd, - sizeof(u32), GFP_KERNEL); - if (!pctrl->power_cfg) + priv->power_cfg = devm_kcalloc(&pdev->dev, pctrl_data->npds, + sizeof(u32), GFP_KERNEL); + if (!priv->power_cfg) return -ENOMEM; - pctrl->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys"); - if (IS_ERR(pctrl->regs[0])) - return PTR_ERR(pctrl->regs[0]); - - pctrl->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc"); - if (IS_ERR(pctrl->regs[1])) - return PTR_ERR(pctrl->regs[1]); - - pctrl->pdesc.name = dev_name(dev); - pctrl->pdesc.pins = pctrl_data->pins; - pctrl->pdesc.npins = pctrl_data->npins; - pctrl->pdesc.pctlops = &cv1800_pctrl_ops; - pctrl->pdesc.pmxops = &cv1800_pmx_ops; - pctrl->pdesc.confops = &cv1800_pconf_ops; - pctrl->pdesc.owner = THIS_MODULE; - - pctrl->data = pctrl_data; - pctrl->dev = dev; - raw_spin_lock_init(&pctrl->lock); - mutex_init(&pctrl->mutex); + priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys"); + if (IS_ERR(priv->regs[0])) + return PTR_ERR(priv->regs[0]); - platform_set_drvdata(pdev, pctrl); + priv->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc"); + if (IS_ERR(priv->regs[1])) + return PTR_ERR(priv->regs[1]); - ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, - pctrl, &pctrl->pctl_dev); - if (ret) - return dev_err_probe(dev, ret, - "fail to register pinctrl driver\n"); + pctrl->priv_ctrl = priv; - return pinctrl_enable(pctrl->pctl_dev); + return 0; } -EXPORT_SYMBOL_GPL(cv1800_pinctrl_probe); + +const struct sophgo_cfg_ops cv1800_cfg_ops = { + .pctrl_init = cv1800_pinctrl_init, + .verify_pinmux_config = cv1800_verify_pinmux_config, + .verify_pin_group = cv1800_verify_pin_group, + .dt_node_to_map_post = cv1800_dt_node_to_map_post, + .compute_pinconf_config = cv1800_pinconf_compute_config, + .set_pinconf_config = cv1800_set_pinconf_config, + .set_pinmux_config = cv1800_set_pinmux_config, +}; +EXPORT_SYMBOL_GPL(cv1800_cfg_ops); diff --git a/drivers/pinctrl/sophgo/pinctrl-cv18xx.h b/drivers/pinctrl/sophgo/pinctrl-cv18xx.h index 1a9998abb3b7..759c0e604acf 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv18xx.h +++ b/drivers/pinctrl/sophgo/pinctrl-cv18xx.h @@ -8,13 +8,14 @@ #include <linux/bits.h> #include <linux/bitfield.h> -#include <linux/device.h> #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf.h> +#include "pinctrl-sophgo.h" + enum cv1800_pin_io_type { IO_TYPE_1V8_ONLY = 0, IO_TYPE_1V8_OR_3V3 = 1, @@ -49,58 +50,37 @@ struct cv1800_pinconf { #define CV1800_PIN_FLAG_IO_TYPE(type) \ FIELD_PREP_CONST(CV1800_PIN_IO_TYPE, type) struct cv1800_pin { - u16 pin; - u16 flags; + struct sophgo_pin pin; u8 power_domain; struct cv1800_pinmux mux; struct cv1800_pinmux2 mux2; struct cv1800_pinconf conf; }; +#define sophgo_to_cv1800_pin(_pin) \ + container_of((_pin), struct cv1800_pin, pin) + #define PIN_POWER_STATE_1V8 1800 #define PIN_POWER_STATE_3V3 3300 -/** - * struct cv1800_vddio_cfg_ops - pin vddio operations - * - * @get_pull_up: get resistor for pull up; - * @get_pull_down: get resistor for pull down. - * @get_oc_map: get mapping for typical low level output current value to - * register value map. - * @get_schmitt_map: get mapping for register value to typical schmitt - * threshold. - */ -struct cv1800_vddio_cfg_ops { - int (*get_pull_up)(struct cv1800_pin *pin, const u32 *psmap); - int (*get_pull_down)(struct cv1800_pin *pin, const u32 *psmap); - int (*get_oc_map)(struct cv1800_pin *pin, const u32 *psmap, - const u32 **map); - int (*get_schmitt_map)(struct cv1800_pin *pin, const u32 *psmap, - const u32 **map); -}; - -struct cv1800_pinctrl_data { - const struct pinctrl_pin_desc *pins; - const struct cv1800_pin *pindata; - const char * const *pdnames; - const struct cv1800_vddio_cfg_ops *vddio_ops; - u16 npins; - u16 npd; -}; - -static inline enum cv1800_pin_io_type cv1800_pin_io_type(struct cv1800_pin *pin) +static inline enum cv1800_pin_io_type cv1800_pin_io_type(const struct cv1800_pin *pin) { - return FIELD_GET(CV1800_PIN_IO_TYPE, pin->flags); + return FIELD_GET(CV1800_PIN_IO_TYPE, pin->pin.flags); }; -int cv1800_pinctrl_probe(struct platform_device *pdev); +extern const struct pinctrl_ops cv1800_pctrl_ops; +extern const struct pinmux_ops cv1800_pmx_ops; +extern const struct pinconf_ops cv1800_pconf_ops; +extern const struct sophgo_cfg_ops cv1800_cfg_ops; #define CV1800_FUNC_PIN(_id, _power_domain, _type, \ _mux_area, _mux_offset, _mux_func_max) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ @@ -112,9 +92,11 @@ int cv1800_pinctrl_probe(struct platform_device *pdev); _mux_area, _mux_offset, _mux_func_max, \ _conf_area, _conf_offset) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ @@ -132,10 +114,12 @@ int cv1800_pinctrl_probe(struct platform_device *pdev); _mux2_func_max, \ _conf_area, _conf_offset) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \ + CV1800_PIN_HAVE_MUX2, \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \ - CV1800_PIN_HAVE_MUX2, \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2000.c b/drivers/pinctrl/sophgo/pinctrl-sg2000.c index 63c05b4dd68f..0e303d2fa104 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2000.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2000.c @@ -40,8 +40,9 @@ static const char *const sg2000_power_domain_desc[] = { [VDDIO_VIVO] = "VDDIO_VIVO", }; -static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int sg2000_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -60,8 +61,9 @@ static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int sg2000_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int sg2000_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -114,9 +116,10 @@ static const u32 sg2000_eth_oc_map[] = { 17800 }; -static int sg2000_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2000_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -159,9 +162,10 @@ static const u32 sg2000_18od33_3v3_schmitt_map[] = { 1100000 }; -static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2000_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -183,11 +187,11 @@ static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops sg2000_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops sg2000_vddio_cfg_ops = { .get_pull_up = sg2000_get_pull_up, .get_pull_down = sg2000_get_pull_down, .get_oc_map = sg2000_get_oc_map, - .get_schmitt_map = sg2000_get_schmitt_map, + .get_schmitt_map = sg2000_get_schmitt_map, }; static const struct pinctrl_pin_desc sg2000_pins[] = { @@ -742,13 +746,18 @@ static const struct cv1800_pin sg2000_pin_data[ARRAY_SIZE(sg2000_pins)] = { CV1800_PINCONF_AREA_RTC, 0x028), }; -static const struct cv1800_pinctrl_data sg2000_pindata = { +static const struct sophgo_pinctrl_data sg2000_pindata = { .pins = sg2000_pins, .pindata = sg2000_pin_data, .pdnames = sg2000_power_domain_desc, .vddio_ops = &sg2000_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(sg2000_pins), - .npd = ARRAY_SIZE(sg2000_power_domain_desc), + .npds = ARRAY_SIZE(sg2000_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id sg2000_pinctrl_ids[] = { @@ -758,7 +767,7 @@ static const struct of_device_id sg2000_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, sg2000_pinctrl_ids); static struct platform_driver sg2000_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "sg2000-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2002.c b/drivers/pinctrl/sophgo/pinctrl-sg2002.c index 5c49208dcb59..2443fff1bc00 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2002.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2002.c @@ -34,8 +34,9 @@ static const char *const sg2002_power_domain_desc[] = { [VDDIO_SD1] = "VDDIO_SD1", }; -static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int sg2002_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -54,8 +55,9 @@ static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int sg2002_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -108,9 +110,10 @@ static const u32 sg2002_eth_oc_map[] = { 17800 }; -static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2002_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -153,9 +156,10 @@ static const u32 sg2002_18od33_3v3_schmitt_map[] = { 1100000 }; -static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2002_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -177,11 +181,11 @@ static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops sg2002_vddio_cfg_ops = { .get_pull_up = sg2002_get_pull_up, .get_pull_down = sg2002_get_pull_down, .get_oc_map = sg2002_get_oc_map, - .get_schmitt_map = sg2002_get_schmitt_map, + .get_schmitt_map = sg2002_get_schmitt_map, }; static const struct pinctrl_pin_desc sg2002_pins[] = { @@ -513,13 +517,18 @@ static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = { CV1800_PINCONF_AREA_SYS, 0xc84), }; -static const struct cv1800_pinctrl_data sg2002_pindata = { +static const struct sophgo_pinctrl_data sg2002_pindata = { .pins = sg2002_pins, .pindata = sg2002_pin_data, .pdnames = sg2002_power_domain_desc, .vddio_ops = &sg2002_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(sg2002_pins), - .npd = ARRAY_SIZE(sg2002_power_domain_desc), + .npds = ARRAY_SIZE(sg2002_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id sg2002_pinctrl_ids[] = { @@ -529,7 +538,7 @@ static const struct of_device_id sg2002_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids); static struct platform_driver sg2002_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "sg2002-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c b/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c new file mode 100644 index 000000000000..0526aa3f8438 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo sg2042 SoCs pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "../pinctrl-utils.h" +#include "../pinmux.h" + +#include "pinctrl-sg2042.h" + +#define PIN_IO_PULL_ONE_ENABLE BIT(0) +#define PIN_IO_PULL_DIR_UP (BIT(1) | PIN_IO_PULL_ONE_ENABLE) +#define PIN_IO_PULL_DIR_DOWN (0 | PIN_IO_PULL_ONE_ENABLE) +#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0) + +#define PIN_IO_PULL_UP BIT(2) +#define PIN_IO_PULL_UP_DONW BIT(3) +#define PIN_IO_PULL_UP_MASK GENMASK(3, 2) + +#define PIN_IO_MUX GENMASK(5, 4) +#define PIN_IO_DRIVE GENMASK(9, 6) +#define PIN_IO_SCHMITT_ENABLE BIT(10) +#define PIN_IO_OUTPUT_ENABLE BIT(11) + +struct sg2042_priv { + void __iomem *regs; +}; + +static u8 sg2042_dt_get_pin_mux(u32 value) +{ + return value >> 16; +} + +static inline u32 sg2042_get_pin_reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp) +{ + struct sg2042_priv *priv = pctrl->priv_ctrl; + const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp); + void __iomem *reg = priv->regs + pin->offset; + + if (sp->flags & PIN_FLAG_WRITE_HIGH) + return readl(reg) >> 16; + else + return readl(reg) & 0xffff; +} + +static int sg2042_set_pin_reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask) +{ + struct sg2042_priv *priv = pctrl->priv_ctrl; + const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp); + void __iomem *reg = priv->regs + pin->offset; + u32 v = readl(reg); + + if (sp->flags & PIN_FLAG_WRITE_HIGH) { + v &= ~(mask << 16); + v |= value << 16; + } else { + v &= ~mask; + v |= value; + } + + writel(v, reg); + + return 0; +} + +static void sg2042_pctrl_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin_id) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + u32 value, mux; + + value = sg2042_get_pin_reg(pctrl, sp); + mux = FIELD_GET(PIN_IO_MUX, value); + seq_printf(seq, "mux:%u reg:0x%04x ", mux, value); +} + +const struct pinctrl_ops sg2042_pctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = sg2042_pctrl_dbg_show, + .dt_node_to_map = sophgo_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; +EXPORT_SYMBOL_GPL(sg2042_pctrl_ops); + +static void sg2042_set_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config) +{ + u32 mux = sg2042_dt_get_pin_mux(config); + + if (!(sp->flags & PIN_FLAG_NO_PINMUX)) + sg2042_set_pin_reg(pctrl, sp, mux, PIN_IO_MUX); +} + +const struct pinmux_ops sg2042_pmx_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = sophgo_pmx_set_mux, + .strict = true, +}; +EXPORT_SYMBOL_GPL(sg2042_pmx_ops); + +static int sg2042_pconf_get(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + u32 value; + u32 arg; + bool enabled; + int ret; + + if (!sp) + return -EINVAL; + + value = sg2042_get_pin_reg(pctrl, sp); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) + arg = FIELD_GET(PIN_IO_PULL_ONE_ENABLE, value); + else + arg = FIELD_GET(PIN_IO_PULL_UP_MASK, value); + enabled = arg == 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value); + enabled = arg == PIN_IO_PULL_DIR_DOWN; + } else { + enabled = FIELD_GET(PIN_IO_PULL_UP_DONW, value) != 0; + } + arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, NULL); + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value); + enabled = arg == PIN_IO_PULL_DIR_UP; + } else { + enabled = FIELD_GET(PIN_IO_PULL_UP, value) != 0; + } + arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, NULL); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + enabled = FIELD_GET(PIN_IO_OUTPUT_ENABLE, value) != 0; + arg = FIELD_GET(PIN_IO_DRIVE, value); + ret = sophgo_pinctrl_reg2oc(pctrl, sp, NULL, arg); + if (ret < 0) + return ret; + arg = ret; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = FIELD_GET(PIN_IO_SCHMITT_ENABLE, value); + enabled = arg != 0; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return enabled ? 0 : -EINVAL; +} + +static int sg2042_pinconf_compute_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + unsigned long *configs, + unsigned int num_configs, + u32 *value, u32 *mask) +{ + int i; + u16 v = 0, m = 0; + int ret; + + if (!sp) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_ENABLE; + m |= PIN_IO_PULL_ONE_ENABLE; + } else { + v &= ~PIN_IO_PULL_UP_MASK; + m |= PIN_IO_PULL_UP_MASK; + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_MASK; + v |= PIN_IO_PULL_DIR_DOWN; + m |= PIN_IO_PULL_ONE_MASK; + } else { + v |= PIN_IO_PULL_UP_DONW; + m |= PIN_IO_PULL_UP_DONW; + } + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_MASK; + v |= PIN_IO_PULL_DIR_UP; + m |= PIN_IO_PULL_ONE_MASK; + } else { + v |= PIN_IO_PULL_UP; + m |= PIN_IO_PULL_UP; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE); + if (arg != 0) { + ret = sophgo_pinctrl_oc2reg(pctrl, sp, NULL, arg); + if (ret < 0) + return ret; + if (!(sp->flags & PIN_FLAG_NO_OEX_EN)) + v |= PIN_IO_OUTPUT_ENABLE; + v |= FIELD_PREP(PIN_IO_DRIVE, ret); + } + m |= PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + v |= PIN_IO_SCHMITT_ENABLE; + m |= PIN_IO_SCHMITT_ENABLE; + break; + default: + return -ENOTSUPP; + } + } + + *value = v; + *mask = m; + + return 0; +} + +const struct pinconf_ops sg2042_pconf_ops = { + .pin_config_get = sg2042_pconf_get, + .pin_config_set = sophgo_pconf_set, + .pin_config_group_set = sophgo_pconf_group_set, + .is_generic = true, +}; +EXPORT_SYMBOL_GPL(sg2042_pconf_ops); + +static int sophgo_pinctrl_init(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl) +{ + struct sg2042_priv *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + pctrl->priv_ctrl = priv; + + return 0; +} + +const struct sophgo_cfg_ops sg2042_cfg_ops = { + .pctrl_init = sophgo_pinctrl_init, + .compute_pinconf_config = sg2042_pinconf_compute_config, + .set_pinconf_config = sg2042_set_pin_reg, + .set_pinmux_config = sg2042_set_pinmux_config, +}; +EXPORT_SYMBOL_GPL(sg2042_cfg_ops); diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042.c b/drivers/pinctrl/sophgo/pinctrl-sg2042.c new file mode 100644 index 000000000000..185305ac897d --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042.c @@ -0,0 +1,655 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 SoC pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/pinctrl-sg2042.h> + +#include "pinctrl-sg2042.h" + +static int sg2042_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 35000; +} + +static int sg2042_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 28000; +} + +static const u32 sg2042_oc_map[] = { + 5400, 8100, 10700, 13400, + 16100, 18800, 21400, 24100, + 26800, 29400, 32100, 34800, + 37400, 40100, 42800, 45400 +}; + +static int sg2042_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, + const u32 **map) +{ + *map = sg2042_oc_map; + return ARRAY_SIZE(sg2042_oc_map); +} + +static const struct sophgo_vddio_cfg_ops sg2042_vddio_cfg_ops = { + .get_pull_up = sg2042_get_pull_up, + .get_pull_down = sg2042_get_pull_down, + .get_oc_map = sg2042_get_oc_map, +}; + +static const struct pinctrl_pin_desc sg2042_pins[] = { + PINCTRL_PIN(PIN_LPC_LCLK, "lpc_lclk"), + PINCTRL_PIN(PIN_LPC_LFRAME, "lpc_lframe"), + PINCTRL_PIN(PIN_LPC_LAD0, "lpc_lad0"), + PINCTRL_PIN(PIN_LPC_LAD1, "lpc_lad1"), + PINCTRL_PIN(PIN_LPC_LAD2, "lpc_lad2"), + PINCTRL_PIN(PIN_LPC_LAD3, "lpc_lad3"), + PINCTRL_PIN(PIN_LPC_LDRQ0, "lpc_ldrq0"), + PINCTRL_PIN(PIN_LPC_LDRQ1, "lpc_ldrq1"), + PINCTRL_PIN(PIN_LPC_SERIRQ, "lpc_serirq"), + PINCTRL_PIN(PIN_LPC_CLKRUN, "lpc_clkrun"), + PINCTRL_PIN(PIN_LPC_LPME, "lpc_lpme"), + PINCTRL_PIN(PIN_LPC_LPCPD, "lpc_lpcpd"), + PINCTRL_PIN(PIN_LPC_LSMI, "lpc_lsmi"), + PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"), + PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"), + PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"), + PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"), + PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"), + PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"), + PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"), + PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"), + PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"), + PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"), + PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"), + PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"), + PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"), + PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"), + PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"), + PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"), + PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"), + PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"), + PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"), + PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"), + PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"), + PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"), + PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"), + PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"), + PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"), + PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"), + PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"), + PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"), + PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"), + PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"), + PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"), + PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"), + PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"), + PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"), + PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"), + PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"), + PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"), + PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"), + PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"), + PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"), + PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"), + PINCTRL_PIN(PIN_PWM0, "pwm0"), + PINCTRL_PIN(PIN_PWM1, "pwm1"), + PINCTRL_PIN(PIN_PWM2, "pwm2"), + PINCTRL_PIN(PIN_PWM3, "pwm3"), + PINCTRL_PIN(PIN_FAN0, "fan0"), + PINCTRL_PIN(PIN_FAN1, "fan1"), + PINCTRL_PIN(PIN_FAN2, "fan2"), + PINCTRL_PIN(PIN_FAN3, "fan3"), + PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"), + PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"), + PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"), + PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"), + PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"), + PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"), + PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"), + PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"), + PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"), + PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"), + PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"), + PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"), + PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"), + PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"), + PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"), + PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"), + PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"), + PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"), + PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"), + PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"), + PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"), + PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"), + PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"), + PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"), + PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"), + PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"), + PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"), + PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"), + PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"), + PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"), + PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"), + PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"), + PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"), + PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"), + PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"), + PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"), + PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"), + PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"), + PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"), + PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"), + PINCTRL_PIN(PIN_GPIO0, "gpio0"), + PINCTRL_PIN(PIN_GPIO1, "gpio1"), + PINCTRL_PIN(PIN_GPIO2, "gpio2"), + PINCTRL_PIN(PIN_GPIO3, "gpio3"), + PINCTRL_PIN(PIN_GPIO4, "gpio4"), + PINCTRL_PIN(PIN_GPIO5, "gpio5"), + PINCTRL_PIN(PIN_GPIO6, "gpio6"), + PINCTRL_PIN(PIN_GPIO7, "gpio7"), + PINCTRL_PIN(PIN_GPIO8, "gpio8"), + PINCTRL_PIN(PIN_GPIO9, "gpio9"), + PINCTRL_PIN(PIN_GPIO10, "gpio10"), + PINCTRL_PIN(PIN_GPIO11, "gpio11"), + PINCTRL_PIN(PIN_GPIO12, "gpio12"), + PINCTRL_PIN(PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PIN_GPIO15, "gpio15"), + PINCTRL_PIN(PIN_GPIO16, "gpio16"), + PINCTRL_PIN(PIN_GPIO17, "gpio17"), + PINCTRL_PIN(PIN_GPIO18, "gpio18"), + PINCTRL_PIN(PIN_GPIO19, "gpio19"), + PINCTRL_PIN(PIN_GPIO20, "gpio20"), + PINCTRL_PIN(PIN_GPIO21, "gpio21"), + PINCTRL_PIN(PIN_GPIO22, "gpio22"), + PINCTRL_PIN(PIN_GPIO23, "gpio23"), + PINCTRL_PIN(PIN_GPIO24, "gpio24"), + PINCTRL_PIN(PIN_GPIO25, "gpio25"), + PINCTRL_PIN(PIN_GPIO26, "gpio26"), + PINCTRL_PIN(PIN_GPIO27, "gpio27"), + PINCTRL_PIN(PIN_GPIO28, "gpio28"), + PINCTRL_PIN(PIN_GPIO29, "gpio29"), + PINCTRL_PIN(PIN_GPIO30, "gpio30"), + PINCTRL_PIN(PIN_GPIO31, "gpio31"), + PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"), + PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"), + PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"), + PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"), + PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"), + PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"), + PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"), + PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"), + PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"), + PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"), + PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"), + PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_L, "pll_clk_in_ddr_l"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_R, "pll_clk_in_ddr_r"), + PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"), + PINCTRL_PIN(PIN_SYS_RST, "sys_rst"), + PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"), + PINCTRL_PIN(PIN_TEST_EN, "test_en"), + PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"), + PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"), + PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"), + PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"), +}; + +static const struct sg2042_pin sg2042_pin_data[ARRAY_SIZE(sg2042_pins)] = { + SG2042_GENERAL_PIN(PIN_LPC_LCLK, 0x000, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LFRAME, 0x000, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD0, 0x004, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD1, 0x004, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD2, 0x008, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD3, 0x008, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LDRQ0, 0x00c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LDRQ1, 0x00c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_SERIRQ, 0x010, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_CLKRUN, 0x010, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LPME, 0x014, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LPCPD, 0x014, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LSMI, 0x018, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x01c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x020, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x024, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x028, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x02c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x030, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x030, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x034, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x034, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x038, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x038, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x03c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x03c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x040, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x040, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x044, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x044, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x048, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x048, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x04c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x04c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x050, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x050, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x054, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x054, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x058, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x058, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x05c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x05c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x060, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x060, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x064, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x064, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x068, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x068, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x06c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x06c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x070, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x070, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x074, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x074, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x078, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x078, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x07c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x07c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x080, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM0, 0x080, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM1, 0x084, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM2, 0x084, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM3, 0x088, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN0, 0x088, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN1, 0x08c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN2, 0x08c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN3, 0x090, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x090, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x094, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x094, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x098, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x098, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x09c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x09c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0a0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0a0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0a4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0a4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0a8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0a8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0ac, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0ac, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0b0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0b0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0b4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0b4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0b8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0b8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0bc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0bc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0c0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0c0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0c4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0c4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0c8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0c8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0cc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0cc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0d0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0d0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0d4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0d4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0d8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0d8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0dc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x0dc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x0e0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x0e0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x0e4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x0e4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x0e8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x0e8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x0ec, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x0ec, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x0f0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x0f0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x0f4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x0f4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x0f8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO0, 0x0f8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO1, 0x0fc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO2, 0x0fc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO3, 0x100, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO4, 0x100, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO5, 0x104, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO6, 0x104, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO7, 0x108, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO8, 0x108, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO9, 0x10c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO10, 0x10c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO11, 0x110, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO12, 0x110, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO13, 0x114, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO14, 0x114, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO15, 0x118, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO16, 0x118, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO17, 0x11c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO18, 0x11c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO19, 0x120, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO20, 0x120, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO21, 0x124, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO22, 0x124, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO23, 0x128, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO24, 0x128, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO25, 0x12c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO26, 0x12c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO27, 0x130, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO28, 0x130, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO29, 0x134, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO30, 0x134, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO31, 0x138, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x138, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x13c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x13c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x140, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x140, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x144, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x144, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x148, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x148, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x14c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x14c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x150, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x150, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x154, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x154, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_L, 0x158, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_R, 0x158, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x15c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SYS_RST, 0x15c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x160, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_EN, 0x160, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x164, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x164, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x168, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x168, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), +}; + +static const struct sophgo_pinctrl_data sg2042_pindata = { + .pins = sg2042_pins, + .pindata = sg2042_pin_data, + .vddio_ops = &sg2042_vddio_cfg_ops, + .cfg_ops = &sg2042_cfg_ops, + .pctl_ops = &sg2042_pctrl_ops, + .pmx_ops = &sg2042_pmx_ops, + .pconf_ops = &sg2042_pconf_ops, + .npins = ARRAY_SIZE(sg2042_pins), + .pinsize = sizeof(struct sg2042_pin), +}; + +static const struct of_device_id sg2042_pinctrl_ids[] = { + { .compatible = "sophgo,sg2042-pinctrl", .data = &sg2042_pindata }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2042_pinctrl_ids); + +static struct platform_driver sg2042_pinctrl_driver = { + .probe = sophgo_pinctrl_probe, + .driver = { + .name = "sg2042-pinctrl", + .suppress_bind_attrs = true, + .of_match_table = sg2042_pinctrl_ids, + }, +}; +module_platform_driver(sg2042_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042.h b/drivers/pinctrl/sophgo/pinctrl-sg2042.h new file mode 100644 index 000000000000..d481973fcf97 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _PINCTRL_SOPHGO_SG2042_H +#define _PINCTRL_SOPHGO_SG2042_H + +#include <linux/bits.h> +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> + +#include "pinctrl-sophgo.h" + +#define PIN_FLAG_DEFAULT 0 +#define PIN_FLAG_WRITE_HIGH BIT(0) +#define PIN_FLAG_ONLY_ONE_PULL BIT(1) +#define PIN_FLAG_NO_PINMUX BIT(2) +#define PIN_FLAG_NO_OEX_EN BIT(3) +#define PIN_FLAG_IS_ETH BIT(4) + +struct sg2042_pin { + struct sophgo_pin pin; + u16 offset; +}; + +#define sophgo_to_sg2042_pin(_pin) \ + container_of((_pin), struct sg2042_pin, pin) + +extern const struct pinctrl_ops sg2042_pctrl_ops; +extern const struct pinmux_ops sg2042_pmx_ops; +extern const struct pinconf_ops sg2042_pconf_ops; +extern const struct sophgo_cfg_ops sg2042_cfg_ops; + +#define SG2042_GENERAL_PIN(_id, _offset, _flag) \ + { \ + .pin = { \ + .id = (_id), \ + .flags = (_flag), \ + }, \ + .offset = (_offset), \ + } + +#endif diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2044.c b/drivers/pinctrl/sophgo/pinctrl-sg2044.c new file mode 100644 index 000000000000..b0c46d8954ca --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2044.c @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 SoC pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/pinctrl-sg2044.h> + +#include "pinctrl-sg2042.h" + +static int sg2044_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 19500; +} + +static int sg2044_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 23200; +} + +static const u32 sg2044_oc_map[] = { + 3200, 6400, 9600, 12700, + 15900, 19100, 22200, 25300, + 29500, 32700, 35900, 39000, + 42000, 45200, 48300, 51400 +}; + +static int sg2044_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, + const u32 **map) +{ + *map = sg2044_oc_map; + return ARRAY_SIZE(sg2044_oc_map); +} + +static const struct sophgo_vddio_cfg_ops sg2044_vddio_cfg_ops = { + .get_pull_up = sg2044_get_pull_up, + .get_pull_down = sg2044_get_pull_down, + .get_oc_map = sg2044_get_oc_map, +}; + +static const struct pinctrl_pin_desc sg2044_pins[] = { + PINCTRL_PIN(PIN_IIC0_SMBSUS_IN, "iic0_smbsus_in"), + PINCTRL_PIN(PIN_IIC0_SMBSUS_OUT, "iic0_smbsus_out"), + PINCTRL_PIN(PIN_IIC0_SMBALERT, "iic0_smbalert"), + PINCTRL_PIN(PIN_IIC1_SMBSUS_IN, "iic1_smbsus_in"), + PINCTRL_PIN(PIN_IIC1_SMBSUS_OUT, "iic1_smbsus_out"), + PINCTRL_PIN(PIN_IIC1_SMBALERT, "iic1_smbalert"), + PINCTRL_PIN(PIN_IIC2_SMBSUS_IN, "iic2_smbsus_in"), + PINCTRL_PIN(PIN_IIC2_SMBSUS_OUT, "iic2_smbsus_out"), + PINCTRL_PIN(PIN_IIC2_SMBALERT, "iic2_smbalert"), + PINCTRL_PIN(PIN_IIC3_SMBSUS_IN, "iic3_smbsus_in"), + PINCTRL_PIN(PIN_IIC3_SMBSUS_OUT, "iic3_smbsus_out"), + PINCTRL_PIN(PIN_IIC3_SMBALERT, "iic3_smbalert"), + PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"), + PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"), + PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"), + PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"), + PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE2_L0_RESET, "pcie2_l0_reset"), + PINCTRL_PIN(PIN_PCIE2_L1_RESET, "pcie2_l1_reset"), + PINCTRL_PIN(PIN_PCIE2_L0_WAKEUP, "pcie2_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE2_L1_WAKEUP, "pcie2_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE2_L0_CLKREQ_IN, "pcie2_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE2_L1_CLKREQ_IN, "pcie2_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE3_L0_RESET, "pcie3_l0_reset"), + PINCTRL_PIN(PIN_PCIE3_L1_RESET, "pcie3_l1_reset"), + PINCTRL_PIN(PIN_PCIE3_L0_WAKEUP, "pcie3_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE3_L1_WAKEUP, "pcie3_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE3_L0_CLKREQ_IN, "pcie3_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE3_L1_CLKREQ_IN, "pcie3_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE4_L0_RESET, "pcie4_l0_reset"), + PINCTRL_PIN(PIN_PCIE4_L1_RESET, "pcie4_l1_reset"), + PINCTRL_PIN(PIN_PCIE4_L0_WAKEUP, "pcie4_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE4_L1_WAKEUP, "pcie4_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE4_L0_CLKREQ_IN, "pcie4_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE4_L1_CLKREQ_IN, "pcie4_l1_clkreq_in"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"), + PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"), + PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"), + PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"), + PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"), + PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"), + PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"), + PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"), + PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"), + PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"), + PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"), + PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"), + PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"), + PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"), + PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"), + PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"), + PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"), + PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"), + PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"), + PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"), + PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"), + PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"), + PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"), + PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"), + PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"), + PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"), + PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"), + PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"), + PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"), + PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"), + PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"), + PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"), + PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"), + PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"), + PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"), + PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"), + PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"), + PINCTRL_PIN(PIN_PWM0, "pwm0"), + PINCTRL_PIN(PIN_PWM1, "pwm1"), + PINCTRL_PIN(PIN_PWM2, "pwm2"), + PINCTRL_PIN(PIN_PWM3, "pwm3"), + PINCTRL_PIN(PIN_FAN0, "fan0"), + PINCTRL_PIN(PIN_FAN1, "fan1"), + PINCTRL_PIN(PIN_FAN2, "fan2"), + PINCTRL_PIN(PIN_FAN3, "fan3"), + PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"), + PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"), + PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"), + PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"), + PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"), + PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"), + PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"), + PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"), + PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"), + PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"), + PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"), + PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"), + PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"), + PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"), + PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"), + PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"), + PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"), + PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"), + PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"), + PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"), + PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"), + PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"), + PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"), + PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"), + PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"), + PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"), + PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"), + PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"), + PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"), + PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"), + PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"), + PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"), + PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"), + PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"), + PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"), + PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"), + PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"), + PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"), + PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"), + PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"), + PINCTRL_PIN(PIN_JTAG3_TDO, "jtag3_tdo"), + PINCTRL_PIN(PIN_JTAG3_TCK, "jtag3_tck"), + PINCTRL_PIN(PIN_JTAG3_TDI, "jtag3_tdi"), + PINCTRL_PIN(PIN_JTAG3_TMS, "jtag3_tms"), + PINCTRL_PIN(PIN_JTAG3_TRST, "jtag3_trst"), + PINCTRL_PIN(PIN_JTAG3_SRST, "jtag3_srst"), + PINCTRL_PIN(PIN_GPIO0, "gpio0"), + PINCTRL_PIN(PIN_GPIO1, "gpio1"), + PINCTRL_PIN(PIN_GPIO2, "gpio2"), + PINCTRL_PIN(PIN_GPIO3, "gpio3"), + PINCTRL_PIN(PIN_GPIO4, "gpio4"), + PINCTRL_PIN(PIN_GPIO5, "gpio5"), + PINCTRL_PIN(PIN_GPIO6, "gpio6"), + PINCTRL_PIN(PIN_GPIO7, "gpio7"), + PINCTRL_PIN(PIN_GPIO8, "gpio8"), + PINCTRL_PIN(PIN_GPIO9, "gpio9"), + PINCTRL_PIN(PIN_GPIO10, "gpio10"), + PINCTRL_PIN(PIN_GPIO11, "gpio11"), + PINCTRL_PIN(PIN_GPIO12, "gpio12"), + PINCTRL_PIN(PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PIN_GPIO15, "gpio15"), + PINCTRL_PIN(PIN_GPIO16, "gpio16"), + PINCTRL_PIN(PIN_GPIO17, "gpio17"), + PINCTRL_PIN(PIN_GPIO18, "gpio18"), + PINCTRL_PIN(PIN_GPIO19, "gpio19"), + PINCTRL_PIN(PIN_GPIO20, "gpio20"), + PINCTRL_PIN(PIN_GPIO21, "gpio21"), + PINCTRL_PIN(PIN_GPIO22, "gpio22"), + PINCTRL_PIN(PIN_GPIO23, "gpio23"), + PINCTRL_PIN(PIN_GPIO24, "gpio24"), + PINCTRL_PIN(PIN_GPIO25, "gpio25"), + PINCTRL_PIN(PIN_GPIO26, "gpio26"), + PINCTRL_PIN(PIN_GPIO27, "gpio27"), + PINCTRL_PIN(PIN_GPIO28, "gpio28"), + PINCTRL_PIN(PIN_GPIO29, "gpio29"), + PINCTRL_PIN(PIN_GPIO30, "gpio30"), + PINCTRL_PIN(PIN_GPIO31, "gpio31"), + PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"), + PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"), + PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"), + PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"), + PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"), + PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"), + PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"), + PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"), + PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"), + PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"), + PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"), + PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_0, "pll_clk_in_ddr_0"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_1, "pll_clk_in_ddr_1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_2, "pll_clk_in_ddr_2"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_3, "pll_clk_in_ddr_3"), + PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"), + PINCTRL_PIN(PIN_SYS_RST, "sys_rst"), + PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"), + PINCTRL_PIN(PIN_TEST_EN, "test_en"), + PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"), + PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"), + PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"), + PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"), +}; + +static const struct sg2042_pin sg2044_pin_data[ARRAY_SIZE(sg2044_pins)] = { + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_IN, 0x000, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_OUT, 0x000, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SMBALERT, 0x004, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_IN, 0x004, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_OUT, 0x008, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SMBALERT, 0x008, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_IN, 0x00c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_OUT, 0x00c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SMBALERT, 0x010, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_IN, 0x010, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_OUT, 0x014, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SMBALERT, 0x014, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x018, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x01c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x020, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x024, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x028, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x02c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_RESET, 0x030, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_RESET, 0x030, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_WAKEUP, 0x034, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_WAKEUP, 0x034, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_CLKREQ_IN, 0x038, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_CLKREQ_IN, 0x038, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_RESET, 0x03c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_RESET, 0x03c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_WAKEUP, 0x040, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_WAKEUP, 0x040, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_CLKREQ_IN, 0x044, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_CLKREQ_IN, 0x044, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_RESET, 0x048, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_RESET, 0x048, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_WAKEUP, 0x04c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_WAKEUP, 0x04c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_CLKREQ_IN, 0x050, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_CLKREQ_IN, 0x050, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x054, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x054, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x058, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x058, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x05c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x05c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x060, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x060, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x064, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x064, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x068, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x068, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x06c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x06c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x070, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x070, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x074, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x074, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x078, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x078, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x07c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x07c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x080, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x080, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x084, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x084, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x088, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x088, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x08c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x08c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x090, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x090, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x094, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x094, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x098, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x098, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x09c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x09c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x0a0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x0a0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PWM0, 0x0a4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM1, 0x0a4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PWM2, 0x0a8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM3, 0x0a8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_FAN0, 0x0ac, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_FAN1, 0x0ac, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_FAN2, 0x0b0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_FAN3, 0x0b0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x0b4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x0b4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x0b8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x0b8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x0bc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x0bc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x0c0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0c0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0c4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0c4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0c8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0c8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0cc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0cc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0d0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0d0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0d4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0d4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0d8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0d8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0dc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0dc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0e0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0e0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0e4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0e4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0e8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0e8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0ec, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0ec, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0f0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0f0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0f4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0f4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0f8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0f8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0fc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0fc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x100, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x100, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x104, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x104, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x108, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x108, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x10c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x10c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x110, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x110, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x114, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x114, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x118, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x118, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TDO, 0x11c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_TCK, 0x11c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TDI, 0x120, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_TMS, 0x120, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TRST, 0x124, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_SRST, 0x124, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO0, 0x128, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO1, 0x128, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO2, 0x12c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO3, 0x12c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO4, 0x130, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO5, 0x130, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO6, 0x134, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO7, 0x134, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO8, 0x138, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO9, 0x138, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO10, 0x13c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO11, 0x13c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO12, 0x140, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO13, 0x140, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO14, 0x144, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO15, 0x144, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO16, 0x148, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO17, 0x148, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO18, 0x14c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO19, 0x14c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO20, 0x150, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO21, 0x150, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO22, 0x154, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO23, 0x154, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO24, 0x158, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO25, 0x158, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO26, 0x15c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO27, 0x15c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO28, 0x160, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO29, 0x160, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO30, 0x164, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO31, 0x164, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x168, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x168, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x16c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x16c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x170, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x170, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x174, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x174, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x178, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x178, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x17c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x17c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x180, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x180, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x184, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_0, 0x184, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_1, 0x188, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_2, 0x188, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_3, 0x18c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x18c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SYS_RST, 0x190, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x190, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_EN, 0x194, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x194, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x198, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x198, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x19c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), +}; + +static const struct sophgo_pinctrl_data sg2044_pindata = { + .pins = sg2044_pins, + .pindata = sg2044_pin_data, + .vddio_ops = &sg2044_vddio_cfg_ops, + .cfg_ops = &sg2042_cfg_ops, + .pctl_ops = &sg2042_pctrl_ops, + .pmx_ops = &sg2042_pmx_ops, + .pconf_ops = &sg2042_pconf_ops, + .npins = ARRAY_SIZE(sg2044_pins), + .pinsize = sizeof(struct sg2042_pin), +}; + +static const struct of_device_id sg2044_pinctrl_ids[] = { + { .compatible = "sophgo,sg2044-pinctrl", .data = &sg2044_pindata }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2044_pinctrl_ids); + +static struct platform_driver sg2044_pinctrl_driver = { + .probe = sophgo_pinctrl_probe, + .driver = { + .name = "sg2044-pinctrl", + .suppress_bind_attrs = true, + .of_match_table = sg2044_pinctrl_ids, + }, +}; +module_platform_driver(sg2044_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c b/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c new file mode 100644 index 000000000000..7f1fd68db19e --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SoCs pinctrl common ops. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#include <linux/bsearch.h> +#include <linux/cleanup.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> + +#include "../pinctrl-utils.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#include "pinctrl-sophgo.h" + +static u16 sophgo_dt_get_pin(u32 value) +{ + return value; +} + +static int sophgo_cmp_pin(const void *key, const void *pivot) +{ + const struct sophgo_pin *pin = pivot; + int pin_id = (long)key; + int pivid = pin->id; + + return pin_id - pivid; +} + +const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl, + unsigned long pin_id) +{ + return bsearch((void *)pin_id, pctrl->data->pindata, pctrl->data->npins, + pctrl->data->pinsize, sophgo_cmp_pin); +} + +static int sophgo_verify_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin_mux_config *config) +{ + if (pctrl->data->cfg_ops->verify_pinmux_config) + return pctrl->data->cfg_ops->verify_pinmux_config(config); + return 0; +} + +static int sophgo_verify_pin_group(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin_mux_config *config, + unsigned int npins) +{ + if (pctrl->data->cfg_ops->verify_pin_group) + return pctrl->data->cfg_ops->verify_pin_group(config, npins); + return 0; +} + +static int sophgo_dt_node_to_map_post(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *config, + unsigned int npins) +{ + if (pctrl->data->cfg_ops->dt_node_to_map_post) + return pctrl->data->cfg_ops->dt_node_to_map_post(cur, pctrl, + config, npins); + return 0; +} + +int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; + struct device_node *child; + struct pinctrl_map *map; + const char **grpnames; + const char *grpname; + int ngroups = 0; + int nmaps = 0; + int ret; + + for_each_available_child_of_node(np, child) + ngroups += 1; + + grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); + if (!grpnames) + return -ENOMEM; + + map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + ngroups = 0; + guard(mutex)(&pctrl->mutex); + for_each_available_child_of_node(np, child) { + int npins = of_property_count_u32_elems(child, "pinmux"); + unsigned int *pins; + struct sophgo_pin_mux_config *pinmuxs; + u32 config; + int i; + + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", + np, child); + ret = -EINVAL; + goto dt_failed; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!grpname) { + ret = -ENOMEM; + goto dt_failed; + } + + grpnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto dt_failed; + } + + pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) { + ret = -ENOMEM; + goto dt_failed; + } + + for (i = 0; i < npins; i++) { + ret = of_property_read_u32_index(child, "pinmux", + i, &config); + if (ret) + goto dt_failed; + + pins[i] = sophgo_dt_get_pin(config); + pinmuxs[i].config = config; + pinmuxs[i].pin = sophgo_get_pin(pctrl, pins[i]); + + if (!pinmuxs[i].pin) { + dev_err(dev, "failed to get pin %d\n", pins[i]); + ret = -ENODEV; + goto dt_failed; + } + + ret = sophgo_verify_pinmux_config(pctrl, &pinmuxs[i]); + if (ret) { + dev_err(dev, "group %s pin %d is invalid\n", + grpname, i); + goto dt_failed; + } + } + + ret = sophgo_verify_pin_group(pctrl, pinmuxs, npins); + if (ret) { + dev_err(dev, "group %s is invalid\n", grpname); + goto dt_failed; + } + + ret = sophgo_dt_node_to_map_post(child, pctrl, pinmuxs, npins); + if (ret) + goto dt_failed; + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "failed to parse pin config of group %s: %d\n", + grpname, ret); + goto dt_failed; + } + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmuxs); + if (ret < 0) { + dev_err(dev, "failed to add group %s: %d\n", grpname, ret); + goto dt_failed; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + grpnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto function_failed; + } + + *maps = map; + *num_maps = nmaps; + + return 0; + +dt_failed: + of_node_put(child); +function_failed: + pinctrl_utils_free_map(pctldev, map, nmaps); + return ret; +} + +int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const struct sophgo_pin_mux_config *configs; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + configs = group->data; + + for (i = 0; i < group->grp.npins; i++) { + const struct sophgo_pin *pin = configs[i].pin; + u32 value = configs[i].config; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + pctrl->data->cfg_ops->set_pinmux_config(pctrl, pin, value); + } + + return 0; +} + +static int sophgo_pin_set_config(struct sophgo_pinctrl *pctrl, + unsigned int pin_id, + u32 value, u32 mask) +{ + const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id); + + if (!pin) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + return pctrl->data->cfg_ops->set_pinconf_config(pctrl, pin, value, mask); +} + +int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id); + u32 value, mask; + + if (!pin) + return -ENODEV; + + if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pin, + configs, num_configs, + &value, &mask)) + return -ENOTSUPP; + + return sophgo_pin_set_config(pctrl, pin_id, value, mask); +} + +int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel, + unsigned long *configs, unsigned int num_configs) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const struct sophgo_pin_mux_config *pinmuxs; + u32 value, mask; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmuxs = group->data; + + if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pinmuxs[0].pin, + configs, num_configs, + &value, &mask)) + return -ENOTSUPP; + + for (i = 0; i < group->grp.npins; i++) + sophgo_pin_set_config(pctrl, group->grp.pins[i], value, mask); + + return 0; +} + +u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg) +{ + return pctrl->data->vddio_ops->get_pull_down(pin, power_cfg); +} + +u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg) +{ + return pctrl->data->vddio_ops->get_pull_up(pin, power_cfg); +} + +int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target) +{ + const u32 *map; + int i, len; + + if (!pctrl->data->vddio_ops->get_oc_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map); + if (len < 0) + return len; + + for (i = 0; i < len; i++) { + if (map[i] >= target) + return i; + } + + return -EINVAL; +} + +int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg) +{ + const u32 *map; + int len; + + if (!pctrl->data->vddio_ops->get_oc_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map); + if (len < 0) + return len; + + if (reg >= len) + return -EINVAL; + + return map[reg]; +} + +int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target) +{ + const u32 *map; + int i, len; + + if (!pctrl->data->vddio_ops->get_schmitt_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map); + if (len < 0) + return len; + + for (i = 0; i < len; i++) { + if (map[i] == target) + return i; + } + + return -EINVAL; +} + +int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg) +{ + const u32 *map; + int len; + + if (!pctrl->data->vddio_ops->get_schmitt_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map); + if (len < 0) + return len; + + if (reg >= len) + return -EINVAL; + + return map[reg]; +} + +int sophgo_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sophgo_pinctrl *pctrl; + const struct sophgo_pinctrl_data *pctrl_data; + int ret; + + pctrl_data = device_get_match_data(dev); + if (!pctrl_data) + return -ENODEV; + + if (pctrl_data->npins == 0) + return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->pdesc.name = dev_name(dev); + pctrl->pdesc.pins = pctrl_data->pins; + pctrl->pdesc.npins = pctrl_data->npins; + pctrl->pdesc.pctlops = pctrl_data->pctl_ops; + pctrl->pdesc.pmxops = pctrl_data->pmx_ops; + pctrl->pdesc.confops = pctrl_data->pconf_ops; + pctrl->pdesc.owner = THIS_MODULE; + + pctrl->data = pctrl_data; + pctrl->dev = dev; + raw_spin_lock_init(&pctrl->lock); + mutex_init(&pctrl->mutex); + + ret = pctrl->data->cfg_ops->pctrl_init(pdev, pctrl); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, + pctrl, &pctrl->pctrl_dev); + if (ret) + return dev_err_probe(dev, ret, + "fail to register pinctrl driver\n"); + + return pinctrl_enable(pctrl->pctrl_dev); +} +EXPORT_SYMBOL_GPL(sophgo_pinctrl_probe); + +MODULE_DESCRIPTION("Common pinctrl helper function for the Sophgo SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo.h b/drivers/pinctrl/sophgo/pinctrl-sophgo.h new file mode 100644 index 000000000000..4cd9b5484894 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _PINCTRL_SOPHGO_H +#define _PINCTRL_SOPHGO_H + +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include "../core.h" + +struct sophgo_pinctrl; + +struct sophgo_pin { + u16 id; + u16 flags; +}; + +struct sophgo_pin_mux_config { + const struct sophgo_pin *pin; + u32 config; +}; + +/** + * struct sophgo_cfg_ops - pin configuration operations + * + * @pctrl_init: soc specific init callback + * @verify_pinmux_config: verify the pinmux config for a pin + * @verify_pin_group: verify the whole pinmux group + * @dt_node_to_map_post: post init for the pinmux config map + * @compute_pinconf_config: compute pinconf config + * @set_pinconf_config: set pinconf config (the caller holds lock) + * @set_pinmux_config: set mux config (the caller holds lock) + */ +struct sophgo_cfg_ops { + int (*pctrl_init)(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl); + int (*verify_pinmux_config)(const struct sophgo_pin_mux_config *config); + int (*verify_pin_group)(const struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins); + int (*dt_node_to_map_post)(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins); + int (*compute_pinconf_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + unsigned long *configs, + unsigned int num_configs, + u32 *value, u32 *mask); + int (*set_pinconf_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask); + void (*set_pinmux_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config); +}; + +/** + * struct sophgo_vddio_cfg_ops - pin vddio operations + * + * @get_pull_up: get resistor for pull up; + * @get_pull_down: get resistor for pull down. + * @get_oc_map: get mapping for typical low level output current value to + * register value map. + * @get_schmitt_map: get mapping for register value to typical schmitt + * threshold. + */ +struct sophgo_vddio_cfg_ops { + int (*get_pull_up)(const struct sophgo_pin *pin, const u32 *psmap); + int (*get_pull_down)(const struct sophgo_pin *pin, const u32 *psmap); + int (*get_oc_map)(const struct sophgo_pin *pin, const u32 *psmap, + const u32 **map); + int (*get_schmitt_map)(const struct sophgo_pin *pin, const u32 *psmap, + const u32 **map); +}; + +struct sophgo_pinctrl_data { + const struct pinctrl_pin_desc *pins; + const void *pindata; + const char * const *pdnames; + const struct sophgo_vddio_cfg_ops *vddio_ops; + const struct sophgo_cfg_ops *cfg_ops; + const struct pinctrl_ops *pctl_ops; + const struct pinmux_ops *pmx_ops; + const struct pinconf_ops *pconf_ops; + u16 npins; + u16 npds; + u16 pinsize; +}; + +struct sophgo_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl_dev; + const struct sophgo_pinctrl_data *data; + struct pinctrl_desc pdesc; + + struct mutex mutex; + raw_spinlock_t lock; + void *priv_ctrl; +}; + +const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl, + unsigned long pin_id); +int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps); +int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel); +int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs); +int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel, + unsigned long *configs, unsigned int num_configs); +u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg); +u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg); +int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target); +int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg); +int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target); +int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg); +int sophgo_pinctrl_probe(struct platform_device *pdev); + +#endif /* _PINCTRL_SOPHGO_H */ |