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-rw-r--r--drivers/gpu/drm/xe/xe_gt.c3
-rw-r--r--drivers/gpu/drm/xe/xe_gt_types.h6
-rw-r--r--drivers/gpu/drm/xe/xe_pci.c4
3 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index fd8232a4556e..96d0f5845d87 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -450,6 +450,9 @@ static int gt_fw_domain_init(struct xe_gt *gt)
if (err)
goto err_force_wake;
+ /* XXX: Fake that we pull the engine mask from hwconfig blob */
+ gt->info.engine_mask = gt->info.__engine_mask;
+
/* Enables per hw engine IRQs */
xe_gt_irq_postinstall(gt);
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index c80a9215098d..2dbc8cedd630 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -93,6 +93,12 @@ struct xe_gt {
u32 clock_freq;
/** @engine_mask: mask of engines present on GT */
u64 engine_mask;
+ /**
+ * @__engine_mask: mask of engines present on GT read from
+ * xe_pci.c, used to fake reading the engine_mask from the
+ * hwconfig blob.
+ */
+ u64 __engine_mask;
} info;
/**
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 55d8a597a068..49f1f0489f1c 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -420,13 +420,13 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (id == 0) {
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.vram_id = id;
- gt->info.engine_mask = desc->platform_engine_mask;
+ gt->info.__engine_mask = desc->platform_engine_mask;
gt->mmio.adj_limit = 0;
gt->mmio.adj_offset = 0;
} else {
gt->info.type = desc->extra_gts[id - 1].type;
gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
- gt->info.engine_mask =
+ gt->info.__engine_mask =
desc->extra_gts[id - 1].engine_mask;
gt->mmio.adj_limit =
desc->extra_gts[id - 1].mmio_adj_limit;