diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 33 |
1 files changed, 11 insertions, 22 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 5c42877fd6fb..8b7a4f7b7576 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -30,13 +30,18 @@ #include <drm/drm_vblank.h> #include "atom.h" +#include "evergreen.h" #include "cik_blit_shaders.h" +#include "cik.h" #include "cikd.h" #include "clearstate_ci.h" +#include "r600.h" #include "radeon.h" #include "radeon_asic.h" #include "radeon_audio.h" #include "radeon_ucode.h" +#include "si.h" +#include "vce.h" #define SH_MEM_CONFIG_GFX_DEFAULT \ ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) @@ -124,21 +129,7 @@ MODULE_FIRMWARE("radeon/mullins_mec.bin"); MODULE_FIRMWARE("radeon/mullins_rlc.bin"); MODULE_FIRMWARE("radeon/mullins_sdma.bin"); -extern int r600_ih_ring_alloc(struct radeon_device *rdev); -extern void r600_ih_ring_fini(struct radeon_device *rdev); -extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); -extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); -extern bool evergreen_is_display_hung(struct radeon_device *rdev); -extern void sumo_rlc_fini(struct radeon_device *rdev); -extern int sumo_rlc_init(struct radeon_device *rdev); -extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); -extern void si_rlc_reset(struct radeon_device *rdev); -extern void si_init_uvd_internal_cg(struct radeon_device *rdev); static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh); -extern int cik_sdma_resume(struct radeon_device *rdev); -extern void cik_sdma_enable(struct radeon_device *rdev, bool enable); -extern void cik_sdma_fini(struct radeon_device *rdev); -extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); static void cik_rlc_stop(struct radeon_device *rdev); static void cik_pcie_gen3_enable(struct radeon_device *rdev); static void cik_program_aspm(struct radeon_device *rdev); @@ -3071,8 +3062,7 @@ static u32 cik_create_bitmask(u32 bit_width) * cik_get_rb_disabled - computes the mask of disabled RBs * * @rdev: radeon_device pointer - * @max_rb_num: max RBs (render backends) for the asic - * @se_num: number of SEs (shader engines) for the asic + * @max_rb_num_per_se: max RBs (render backends) per SE (shader engine) for the asic * @sh_per_se: number of SH blocks per SE for the asic * * Calculates the bitmask of disabled RBs (CIK). @@ -3104,7 +3094,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev, * @rdev: radeon_device pointer * @se_num: number of SEs (shader engines) for the asic * @sh_per_se: number of SH blocks per SE for the asic - * @max_rb_num: max RBs (render backends) for the asic + * @max_rb_num_per_se: max RBs (render backends) per SE for the asic * * Configures per-SE/SH RB registers (CIK). */ @@ -3178,7 +3168,7 @@ static void cik_setup_rb(struct radeon_device *rdev, static void cik_gpu_init(struct radeon_device *rdev) { u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); - u32 mc_shared_chmap, mc_arb_ramcfg; + u32 mc_arb_ramcfg; u32 hdp_host_path_cntl; u32 tmp; int i, j; @@ -3271,7 +3261,7 @@ static void cik_gpu_init(struct radeon_device *rdev) WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); - mc_shared_chmap = RREG32(MC_SHARED_CHMAP); + RREG32(MC_SHARED_CHMAP); mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; @@ -5654,6 +5644,7 @@ void cik_vm_fini(struct radeon_device *rdev) * @rdev: radeon_device pointer * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value + * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value * * Print human readable fault information (CIK). */ @@ -5677,11 +5668,9 @@ static void cik_vm_decode_fault(struct radeon_device *rdev, block, mc_client, mc_id); } -/** +/* * cik_vm_flush - cik vm flush using the CP * - * @rdev: radeon_device pointer - * * Update the page table base and flush the VM TLB * using the CP (CIK). */ |