diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 67 |
1 files changed, 63 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..59c22beaf1de 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -9,6 +9,11 @@ #include "i915_reg_defs.h" #include "intel_display_limits.h" +/* DDI Buffer Control */ +#define _DDI_CLK_VALFREQ_A 0x64030 +#define _DDI_CLK_VALFREQ_B 0x64130 +#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) + /* * Wrapper macro to convert from port number to the index used in some of the * registers. For Display version 20 and above it converts the port number to a @@ -105,7 +110,8 @@ #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) #define XELPDP_TCSS_POWER_STATE REG_BIT(4) #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) -#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) +#define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ _XELPDP_PORT_BUF_CTL1_LN0_A, \ @@ -186,8 +192,17 @@ #define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) #define XELPDP_TBT_CLOCK_ACK REG_BIT(18) -#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) -#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val) +#define _XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) +#define _XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) +#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \ + _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK) +#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \ + REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ + REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) +#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \ + REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ + REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) + #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 @@ -195,17 +210,50 @@ #define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd #define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe #define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf +#define XELPDP_DDI_CLOCK_SELECT_TBT_312_5 0x18 +#define XELPDP_DDI_CLOCK_SELECT_TBT_625 0x19 #define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10) #define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8) #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) +#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) +#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) +#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) +#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val) + +#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) + /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) +#define C10_PLL0_SSC_EN REG_BIT8(0) +#define C10_PLL0_DIVCLK_EN REG_BIT8(1) +#define C10_PLL0_DIV5CLK_EN REG_BIT8(2) +#define C10_PLL0_WORDDIV2_EN REG_BIT8(3) #define C10_PLL0_FRACEN REG_BIT8(4) +#define C10_PLL0_PMIX_EN REG_BIT8(5) +#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6) +#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0) +#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0) #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) +#define C10_PLL8_SSC_UP_SPREAD REG_BIT8(5) +#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0) +#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0) +#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0) +#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0) #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) +#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6) +#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0) +#define C10_PLL16_ANA_CPINTGS_L REG_BIT8(7) +#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0) +#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6) +#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0) +#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5) +#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0) +#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4) #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) @@ -273,13 +321,21 @@ #define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 #define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 -#define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) +#define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401) #define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) +#define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0) +#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) +#define C20_PHY_TX_DCC_CAL_RANGE_MASK REG_GENMASK16(11, 8) +#define C20_PHY_TX_DCC_CAL_RANGE(val) \ + REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val)) +#define C20_PHY_TX_DCC_BYPASS REG_BIT(12) +#define C20_PHY_TX_TERM_CTL_MASK REG_GENMASK16(15, 13) +#define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val)) #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) @@ -363,4 +419,7 @@ #define HDMI_DIV_MASK REG_GENMASK16(2, 0) #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) +#define EDP_ON_TYPEC REG_BIT(31) + #endif /* __INTEL_CX0_REG_DEFS_H__ */ |